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[156.19.246.23]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad90c173sm13338940b3a.192.2024.12.26.14.05.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Dec 2024 14:05:21 -0800 (PST) Message-ID: Date: Thu, 26 Dec 2024 14:05:19 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 14/23] target/loongarch: Scrutinise TCG arithmetic translation for 32 bit build To: Jiaxun Yang , qemu-devel@nongnu.org Cc: Song Gao , Bibo Mao , Eric Blake , Markus Armbruster , Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Yanan Wang , Zhao Liu , Paolo Bonzini References: <20241226-la32-fixes1-v2-0-0414594f8cb5@flygoat.com> <20241226-la32-fixes1-v2-14-0414594f8cb5@flygoat.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20241226-la32-fixes1-v2-14-0414594f8cb5@flygoat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/26/24 13:19, Jiaxun Yang wrote: > mulh.w and mulh.wu are handled with tcg_gen_muls2_i32 and tcg_gen_mulu2_i32 > to adopt different TARGET_LONG size. > > min value of divisor is generated from TARGET_LONG_BITS to adopt different > long size as well. > > Signed-off-by: Jiaxun Yang > --- > target/loongarch/tcg/insn_trans/trans_arith.c.inc | 25 +++++++++++++++++++---- > 1 file changed, 21 insertions(+), 4 deletions(-) > > diff --git a/target/loongarch/tcg/insn_trans/trans_arith.c.inc b/target/loongarch/tcg/insn_trans/trans_arith.c.inc > index 2be057e9320a9b722c173b0352e1631543147d68..a2360c5fdd2003ca0e458743348e687987f421d4 100644 > --- a/target/loongarch/tcg/insn_trans/trans_arith.c.inc > +++ b/target/loongarch/tcg/insn_trans/trans_arith.c.inc > @@ -92,8 +92,24 @@ static void gen_sltu(TCGv dest, TCGv src1, TCGv src2) > > static void gen_mulh_w(TCGv dest, TCGv src1, TCGv src2) > { > - tcg_gen_mul_i64(dest, src1, src2); > - tcg_gen_sari_i64(dest, dest, 32); > +#ifdef TARGET_LOONGARCH64 > + tcg_gen_mul_tl(dest, src1, src2); > + tcg_gen_sari_tl(dest, dest, 32); Leave the _i64. > +#else > + TCGv_i32 discard = tcg_temp_new_i32(); > + tcg_gen_muls2_i32(discard, dest, src1, src2); > +#endif > +} > + > +static void gen_mulh_wu(TCGv dest, TCGv src1, TCGv src2) > +{ > +#ifdef TARGET_LOONGARCH64 > + /* Signs are handled by the caller's EXT_ZERO */ > + gen_mulh_w(dest, src1, src2); > +#else > + TCGv_i32 discard = tcg_temp_new_i32(); > + tcg_gen_mulu2_i32(discard, dest, src1, src2); > +#endif > } Otherwise, these two are fine. > > static void gen_mulh_d(TCGv dest, TCGv src1, TCGv src2) > @@ -113,6 +129,7 @@ static void prep_divisor_d(TCGv ret, TCGv src1, TCGv src2) > TCGv t0 = tcg_temp_new(); > TCGv t1 = tcg_temp_new(); > TCGv zero = tcg_constant_tl(0); > + target_long min = 1ull << (TARGET_LONG_BITS - 1); > > /* > * If min / -1, set the divisor to 1. > @@ -121,7 +138,7 @@ static void prep_divisor_d(TCGv ret, TCGv src1, TCGv src2) > * This avoids potential host overflow trap; > * the required result is undefined. > */ > - tcg_gen_setcondi_tl(TCG_COND_EQ, ret, src1, INT64_MIN); > + tcg_gen_setcondi_tl(TCG_COND_EQ, ret, src1, min); > tcg_gen_setcondi_tl(TCG_COND_EQ, t0, src2, -1); > tcg_gen_setcondi_tl(TCG_COND_EQ, t1, src2, 0); > tcg_gen_and_tl(ret, ret, t0); This is ok, but s/prep_divisor_d/prep_divisor_tl/. Without the rename, this change would appear to affect correctness. In addition, gen_{div,rem}_w will need to use prep_divisor_tl instead of prep_divisor_du. r~