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Tue, 09 Nov 2021 08:44:14 -0800 (PST) Message-ID: Date: Tue, 9 Nov 2021 13:44:11 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.0 Subject: Re: [PATCH 2/2] target/ppc: ppc_store_fpscr doesn't update bit 52 Content-Language: en-US To: "Lucas Mateus Castro (alqotel)" , qemu-devel@nongnu.org, qemu-ppc@nongnu.org References: <20211020125724.78028-1-lucas.araujo@eldorado.org.br> <20211020125724.78028-3-lucas.araujo@eldorado.org.br> From: Daniel Henrique Barboza In-Reply-To: <20211020125724.78028-3-lucas.araujo@eldorado.org.br> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::22a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-3.364, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Lucas Mateus Castro \(alqotel\)" , richard.henderson@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/20/21 09:57, Lucas Mateus Castro (alqotel) wrote: > From: "Lucas Mateus Castro (alqotel)" > > This commit fixes the difference reported in the bug in the reserved > bit 52, it does this by adding this bit to the mask of bits to not be > directly altered in the ppc_store_fpscr function (the hardware used to > compare to QEMU was a Power9). IIUC, "bug" here is related to https://gitlab.com/qemu-project/qemu/-/issues/266, the bug mentioned in the commit msg of the first patch. In that case, you should mention it again in this commit message explicitly. In fact, I also believe that the "Resolves:" tag from the first patch should be moved to this patch instead, given that the bug is only fully fixed after both patches are applied. > > Although this is a difference reported in the bug, since it's a reserved > bit it may be a "don't care" case, as put in the bug report. Looking at > the ISA it doesn't explicitly mentions this bit can't be set, like it > does for FEX and VX, so I'm unsure if this is necessary. > > Signed-off-by: Lucas Mateus Castro (alqotel) > --- > target/ppc/cpu.c | 2 +- > target/ppc/cpu.h | 3 +++ > 2 files changed, 4 insertions(+), 1 deletion(-) > > diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c > index 7ad9bd6044..5c411b32ff 100644 > --- a/target/ppc/cpu.c > +++ b/target/ppc/cpu.c > @@ -112,7 +112,7 @@ static inline void fpscr_set_rounding_mode(CPUPPCState *env) > > void ppc_store_fpscr(CPUPPCState *env, target_ulong val) > { > - val &= ~(FP_VX | FP_FEX); > + val &= FPSCR_MTFS_MASK; > if (val & FPSCR_IX) { > val |= FP_VX; > } > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index baa4e7c34d..4b42b281ed 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -736,6 +736,9 @@ enum { > FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \ > FP_VXSQRT | FP_VXCVI) > > +/* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */ > +#define FPSCR_MTFS_MASK ~((1ull << 11) | FP_VX | FP_FEX) ./scripts/checkpatch.pl is not happy about this line: ERROR: Macros with complex values should be enclosed in parenthesis #44: FILE: target/ppc/cpu.h:763: +#define FPSCR_MTFS_MASK ~((1ull << 11) | FP_VX | FP_FEX) total: 1 errors, 0 warnings, 17 lines checked Thanks, Daniel > + > /*****************************************************************************/ > /* Vector status and control register */ > #define VSCR_NJ 16 /* Vector non-java */ >