From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: David Gibson <david@gibson.dropbear.id.au>,
qemu-ppc@nongnu.org, clg@kaod.org, qemu-devel@nongnu.org,
groug@kaod.org
Cc: lvivier@redhat.com, Thomas Huth <thuth@redhat.com>,
Xiao Guangrong <xiaoguangrong.eric@gmail.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
aik@ozlabs.ru, farosas@linux.ibm.com,
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
Igor Mammedov <imammedo@redhat.com>,
paulus@samba.org, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [PATCH v7 08/17] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS]
Date: Thu, 5 Mar 2020 09:53:30 +0100 [thread overview]
Message-ID: <a760a28a-c7e5-ad00-544c-57075ffbdd65@redhat.com> (raw)
In-Reply-To: <20200303034351.333043-9-david@gibson.dropbear.id.au>
On 3/3/20 4:43 AM, David Gibson wrote:
> Currently we use a big switch statement in ppc_hash64_update_rmls() to work
> out what the right RMA limit is based on the LPCR[RMLS] field. There's no
> formula for this - it's just an arbitrary mapping defined by the existing
> CPU implementations - but we can make it a bit more readable by using a
> lookup table rather than a switch. In addition we can use the MiB/GiB
> symbols to make it a bit clearer.
>
> While there we add a bit of clarity and rationale to the comment about
> what happens if the LPCR[RMLS] doesn't contain a valid value.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> target/ppc/mmu-hash64.c | 63 ++++++++++++++++++-----------------------
> 1 file changed, 27 insertions(+), 36 deletions(-)
>
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index 0ef330a614..934989e6d9 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -18,6 +18,7 @@
> * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> */
> #include "qemu/osdep.h"
> +#include "qemu/units.h"
> #include "cpu.h"
> #include "exec/exec-all.h"
> #include "exec/helper-proto.h"
> @@ -757,6 +758,31 @@ static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1)
> stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80);
> }
>
> +static target_ulong rmls_limit(PowerPCCPU *cpu)
> +{
> + CPUPPCState *env = &cpu->env;
> + /*
> + * This is the full 4 bits encoding of POWER8. Previous
> + * CPUs only support a subset of these but the filtering
> + * is done when writing LPCR.
> + *
> + * Unsupported values mean the OS has shot itself in the
> + * foot. Return a 0-sized RMA in this case, which we expect
> + * to trigger an immediate DSI or ISI
Maybe use qemu_log(GUEST_ERROR) then? (as a follow-up patch).
> + */
> + static const target_ulong rma_sizes[16] = {
> + [1] = 16 * GiB,
> + [2] = 1 * GiB,
> + [3] = 64 * MiB,
> + [4] = 256 * MiB,
> + [7] = 128 * MiB,
> + [8] = 32 * MiB,
> + };
> + target_ulong rmls = (env->spr[SPR_LPCR] & LPCR_RMLS) >> LPCR_RMLS_SHIFT;
> +
> + return rma_sizes[rmls];
> +}
> +
> int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
> int rwx, int mmu_idx)
> {
> @@ -1006,41 +1032,6 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
> cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
> }
>
> -static void ppc_hash64_update_rmls(PowerPCCPU *cpu)
> -{
> - CPUPPCState *env = &cpu->env;
> - uint64_t lpcr = env->spr[SPR_LPCR];
> -
> - /*
> - * This is the full 4 bits encoding of POWER8. Previous
> - * CPUs only support a subset of these but the filtering
> - * is done when writing LPCR
> - */
> - switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) {
> - case 0x8: /* 32MB */
> - env->rmls = 0x2000000ull;
> - break;
> - case 0x3: /* 64MB */
> - env->rmls = 0x4000000ull;
> - break;
> - case 0x7: /* 128MB */
> - env->rmls = 0x8000000ull;
> - break;
> - case 0x4: /* 256MB */
> - env->rmls = 0x10000000ull;
> - break;
> - case 0x2: /* 1GB */
> - env->rmls = 0x40000000ull;
> - break;
> - case 0x1: /* 16GB */
> - env->rmls = 0x400000000ull;
> - break;
> - default:
> - /* What to do here ??? */
> - env->rmls = 0;
> - }
Good refactor.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> -}
> -
> static void ppc_hash64_update_vrma(PowerPCCPU *cpu)
> {
> CPUPPCState *env = &cpu->env;
> @@ -1099,7 +1090,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
> CPUPPCState *env = &cpu->env;
>
> env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
> - ppc_hash64_update_rmls(cpu);
> + env->rmls = rmls_limit(cpu);
> ppc_hash64_update_vrma(cpu);
> }
>
>
next prev parent reply other threads:[~2020-03-05 8:54 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-03 3:43 [PATCH v7 00/17] target/ppc: Correct some errors with real mode handling David Gibson
2020-03-03 3:43 ` [PATCH v7 01/17] ppc: Remove stub support for 32-bit hypervisor mode David Gibson
2020-03-05 8:58 ` Philippe Mathieu-Daudé
2020-03-03 3:43 ` [PATCH v7 02/17] ppc: Remove stub of PPC970 HID4 implementation David Gibson
2020-03-03 3:43 ` [PATCH v7 03/17] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU David Gibson
2020-03-03 3:43 ` [PATCH v7 04/17] target/ppc: Introduce ppc_hash64_use_vrma() helper David Gibson
2020-03-05 8:59 ` Philippe Mathieu-Daudé
2020-03-03 3:43 ` [PATCH v7 05/17] spapr, ppc: Remove VPM0/RMLS hacks for POWER9 David Gibson
2020-03-03 3:43 ` [PATCH v7 06/17] target/ppc: Remove RMOR register from POWER9 & POWER10 David Gibson
2020-03-03 3:43 ` [PATCH v7 07/17] target/ppc: Use class fields to simplify LPCR masking David Gibson
2020-03-05 8:56 ` Philippe Mathieu-Daudé
2020-03-10 10:06 ` Cédric Le Goater
2020-03-11 3:15 ` David Gibson
2020-03-03 3:43 ` [PATCH v7 08/17] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] David Gibson
2020-03-03 7:52 ` Greg Kurz
2020-03-05 8:53 ` Philippe Mathieu-Daudé [this message]
2020-03-03 3:43 ` [PATCH v7 09/17] target/ppc: Correct RMLS table David Gibson
2020-03-03 3:43 ` [PATCH v7 10/17] target/ppc: Only calculate RMLS derived RMA limit on demand David Gibson
2020-03-03 8:57 ` Greg Kurz
2020-03-05 8:48 ` Philippe Mathieu-Daudé
2020-03-03 3:43 ` [PATCH v7 11/17] target/ppc: Don't store VRMA SLBE persistently David Gibson
2020-03-03 9:37 ` Greg Kurz
2020-03-05 9:17 ` Philippe Mathieu-Daudé
2020-03-05 9:47 ` Greg Kurz
2020-03-05 10:35 ` Philippe Mathieu-Daudé
2020-03-03 3:43 ` [PATCH v7 12/17] spapr: Don't use weird units for MIN_RMA_SLOF David Gibson
2020-03-05 8:39 ` Philippe Mathieu-Daudé
2020-03-03 3:43 ` [PATCH v7 13/17] spapr,ppc: Simplify signature of kvmppc_rma_size() David Gibson
2020-03-05 8:47 ` Philippe Mathieu-Daudé
2020-03-03 3:43 ` [PATCH v7 14/17] spapr: Don't attempt to clamp RMA to VRMA constraint David Gibson
2020-03-03 9:55 ` Greg Kurz
2020-03-03 3:43 ` [PATCH v7 15/17] spapr: Don't clamp RMA to 16GiB on new machine types David Gibson
2020-03-03 10:02 ` Greg Kurz
2020-03-05 8:45 ` Philippe Mathieu-Daudé
2020-03-03 3:43 ` [PATCH v7 16/17] spapr: Clean up RMA size calculation David Gibson
2020-03-03 10:18 ` Greg Kurz
2020-03-05 8:43 ` Philippe Mathieu-Daudé
2020-03-03 3:43 ` [PATCH v7 17/17] spapr: Fold spapr_node0_size() into its only caller David Gibson
2020-03-03 10:32 ` Greg Kurz
2020-03-04 1:25 ` David Gibson
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