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[88.21.205.47]) by smtp.gmail.com with ESMTPSA id i17sm563750edj.72.2020.03.05.00.53.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Mar 2020 00:53:31 -0800 (PST) Subject: Re: [PATCH v7 08/17] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] To: David Gibson , qemu-ppc@nongnu.org, clg@kaod.org, qemu-devel@nongnu.org, groug@kaod.org References: <20200303034351.333043-1-david@gibson.dropbear.id.au> <20200303034351.333043-9-david@gibson.dropbear.id.au> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Thu, 5 Mar 2020 09:53:30 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200303034351.333043-9-david@gibson.dropbear.id.au> Content-Language: en-US X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, farosas@linux.ibm.com, Mark Cave-Ayland , Igor Mammedov , paulus@samba.org, "Edgar E. Iglesias" , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/3/20 4:43 AM, David Gibson wrote: > Currently we use a big switch statement in ppc_hash64_update_rmls() to wo= rk > out what the right RMA limit is based on the LPCR[RMLS] field. There's n= o > formula for this - it's just an arbitrary mapping defined by the existing > CPU implementations - but we can make it a bit more readable by using a > lookup table rather than a switch. In addition we can use the MiB/GiB > symbols to make it a bit clearer. >=20 > While there we add a bit of clarity and rationale to the comment about > what happens if the LPCR[RMLS] doesn't contain a valid value. >=20 > Signed-off-by: David Gibson > Reviewed-by: C=C3=A9dric Le Goater > --- > target/ppc/mmu-hash64.c | 63 ++++++++++++++++++----------------------- > 1 file changed, 27 insertions(+), 36 deletions(-) >=20 > diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c > index 0ef330a614..934989e6d9 100644 > --- a/target/ppc/mmu-hash64.c > +++ b/target/ppc/mmu-hash64.c > @@ -18,6 +18,7 @@ > * License along with this library; if not, see . > */ > #include "qemu/osdep.h" > +#include "qemu/units.h" > #include "cpu.h" > #include "exec/exec-all.h" > #include "exec/helper-proto.h" > @@ -757,6 +758,31 @@ static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr= ptex, uint64_t pte1) > stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80); > } > =20 > +static target_ulong rmls_limit(PowerPCCPU *cpu) > +{ > + CPUPPCState *env =3D &cpu->env; > + /* > + * This is the full 4 bits encoding of POWER8. Previous > + * CPUs only support a subset of these but the filtering > + * is done when writing LPCR. > + * > + * Unsupported values mean the OS has shot itself in the > + * foot. Return a 0-sized RMA in this case, which we expect > + * to trigger an immediate DSI or ISI Maybe use qemu_log(GUEST_ERROR) then? (as a follow-up patch). > + */ > + static const target_ulong rma_sizes[16] =3D { > + [1] =3D 16 * GiB, > + [2] =3D 1 * GiB, > + [3] =3D 64 * MiB, > + [4] =3D 256 * MiB, > + [7] =3D 128 * MiB, > + [8] =3D 32 * MiB, > + }; > + target_ulong rmls =3D (env->spr[SPR_LPCR] & LPCR_RMLS) >> LPCR_RMLS_= SHIFT; > + > + return rma_sizes[rmls]; > +} > + > int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, > int rwx, int mmu_idx) > { > @@ -1006,41 +1032,6 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, ta= rget_ulong ptex, > cpu->env.tlb_need_flush =3D TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_= FLUSH; > } > =20 > -static void ppc_hash64_update_rmls(PowerPCCPU *cpu) > -{ > - CPUPPCState *env =3D &cpu->env; > - uint64_t lpcr =3D env->spr[SPR_LPCR]; > - > - /* > - * This is the full 4 bits encoding of POWER8. Previous > - * CPUs only support a subset of these but the filtering > - * is done when writing LPCR > - */ > - switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) { > - case 0x8: /* 32MB */ > - env->rmls =3D 0x2000000ull; > - break; > - case 0x3: /* 64MB */ > - env->rmls =3D 0x4000000ull; > - break; > - case 0x7: /* 128MB */ > - env->rmls =3D 0x8000000ull; > - break; > - case 0x4: /* 256MB */ > - env->rmls =3D 0x10000000ull; > - break; > - case 0x2: /* 1GB */ > - env->rmls =3D 0x40000000ull; > - break; > - case 0x1: /* 16GB */ > - env->rmls =3D 0x400000000ull; > - break; > - default: > - /* What to do here ??? */ > - env->rmls =3D 0; > - } Good refactor. Reviewed-by: Philippe Mathieu-Daud=C3=A9 > -} > - > static void ppc_hash64_update_vrma(PowerPCCPU *cpu) > { > CPUPPCState *env =3D &cpu->env; > @@ -1099,7 +1090,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong v= al) > CPUPPCState *env =3D &cpu->env; > =20 > env->spr[SPR_LPCR] =3D val & pcc->lpcr_mask; > - ppc_hash64_update_rmls(cpu); > + env->rmls =3D rmls_limit(cpu); > ppc_hash64_update_vrma(cpu); > } > =20 >=20