From: Andrew Jeffery <andrew@codeconstruct.com.au>
To: "Jamin Lin" <jamin_lin@aspeedtech.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>, "Joel Stanley" <joel@jms.id.au>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: troy_lee@aspeedtech.com, yunlin.tang@aspeedtech.com
Subject: Re: [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0
Date: Thu, 30 Jan 2025 13:57:59 +1030 [thread overview]
Message-ID: <a79adeedb42dd323f4b6dc0b02b3e4efe1edea92.camel@codeconstruct.com.au> (raw)
In-Reply-To: <20250121070424.2465942-2-jamin_lin@aspeedtech.com>
On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote:
> The design of the INTC has significant changes in the AST2700 A1. In
> the
> AST2700 A0, there was one INTC controller, whereas in the AST2700 A1,
> there were two INTC controllers: INTC0 (CPU DIE) and INTC1 (I/O DIE).
>
> The previous INTC model only supported the AST2700 A0 and was
> implemented for
> the INTC0 (CPU DIE). To support the future INTC1 (I/O DIE) model,
> rename INTC
> to INTC0.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> hw/arm/aspeed_ast27x0.c | 6 +--
> hw/intc/aspeed_intc.c | 90 +++++++++++++++++----------------
> --
> include/hw/arm/aspeed_soc.h | 2 +-
> include/hw/intc/aspeed_intc.h | 2 +-
> 4 files changed, 50 insertions(+), 50 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 4114e15ddd..ba461fcd3c 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -56,7 +56,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_ETH2] = 0x14060000,
> [ASPEED_DEV_ETH3] = 0x14070000,
> [ASPEED_DEV_EMMC] = 0x12090000,
> - [ASPEED_DEV_INTC] = 0x12100000,
> + [ASPEED_DEV_INTC0] = 0x12100000,
> [ASPEED_DEV_SLI] = 0x12C17000,
> [ASPEED_DEV_SLIIO] = 0x14C1E000,
> [ASPEED_GIC_DIST] = 0x12200000,
> @@ -372,7 +372,7 @@ static void aspeed_soc_ast2700_init(Object *obj)
>
> object_initialize_child(obj, "sli", &s->sli,
> TYPE_ASPEED_2700_SLI);
> object_initialize_child(obj, "sliio", &s->sliio,
> TYPE_ASPEED_2700_SLIIO);
> - object_initialize_child(obj, "intc", &a->intc,
> TYPE_ASPEED_2700_INTC);
> + object_initialize_child(obj, "intc", &a->intc,
> TYPE_ASPEED_2700_INTC0);
Shouldn't we also change the propname to "intc0" (... if we're to
continue with that style of naming)?
Andrew
next prev parent reply other threads:[~2025-01-30 3:28 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-21 7:04 [PATCH v1 00/18] Support AST2700 A1 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 01/18] hw/intc/aspeed: Rename INTC to INTC0 Jamin Lin via
2025-01-29 17:03 ` Cédric Le Goater
2025-01-30 3:22 ` Andrew Jeffery
2025-02-04 6:50 ` Jamin Lin
2025-02-04 7:34 ` Cédric Le Goater
2025-02-04 8:22 ` Jamin Lin
2025-02-04 10:26 ` Cédric Le Goater
2025-01-30 3:27 ` Andrew Jeffery [this message]
2025-01-21 7:04 ` [PATCH v1 02/18] hw/intc/aspeed: Support different memory region ops Jamin Lin via
2025-01-30 3:32 ` Andrew Jeffery
2025-02-04 7:00 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 03/18] hw/intc/aspeed: Introduce a new aspeed_2700_intc0_ops for INTC0 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 04/18] hw/intc/aspeed: Support setting different memory and register size Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 05/18] hw/intc/aspeed: Introduce helper functions for enable and status registers Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 06/18] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Jamin Lin via
2025-01-30 3:55 ` Andrew Jeffery
2025-02-04 9:45 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 07/18] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 08/18] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 09/18] hw/intc/aspeed: Add ID to trace events for better debugging Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 10/18] hw/intc/aspeed: Add Support for AST2700 INTC1 Controller Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 11/18] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions Jamin Lin via
2025-01-30 4:05 ` Andrew Jeffery
2025-02-04 7:23 ` Jamin Lin
2025-02-04 7:29 ` Cédric Le Goater
2025-01-21 7:04 ` [PATCH v1 12/18] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Jamin Lin via
2025-01-30 4:19 ` Andrew Jeffery
2025-02-04 9:43 ` Jamin Lin
2025-02-05 3:50 ` Andrew Jeffery
2025-02-05 7:12 ` Jamin Lin
2025-02-05 23:39 ` Andrew Jeffery
2025-02-06 4:55 ` Joel Stanley
2025-02-06 5:15 ` Jamin Lin
2025-02-06 7:17 ` Cédric Le Goater
2025-02-06 7:22 ` Jamin Lin
2025-02-06 7:22 ` Cédric Le Goater
2025-02-06 7:24 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 13/18] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 14/18] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1 Jamin Lin via
2025-01-30 4:22 ` Andrew Jeffery
2025-02-03 8:55 ` Jamin Lin
2025-01-21 7:04 ` [PATCH v1 15/18] hw/misc/aspeed_hace: Fix coding style Jamin Lin via
2025-01-21 7:04 ` [PATCH v1 16/18] hw/misc/aspeed_hace: Add AST2700 support Jamin Lin via
2025-01-30 4:30 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 17/18] hw/arm/aspeed_ast27x0: Add HACE support for AST2700 Jamin Lin via
2025-01-30 4:32 ` Andrew Jeffery
2025-01-21 7:04 ` [PATCH v1 18/18] hw/misc/aspeed_hace: (DROP) Fix boot issue in the Crypto Manager Self Test(WORKAROUND) Jamin Lin via
2025-01-31 7:34 ` [PATCH v1 00/18] Support AST2700 A1 Cédric Le Goater
2025-02-04 8:05 ` Jamin Lin
2025-06-30 20:28 ` Cédric Le Goater
2025-07-02 1:57 ` Jamin Lin
2025-07-02 6:43 ` Cédric Le Goater
2025-07-03 7:43 ` Jamin Lin
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