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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-475dd02ce46sm152237065e9.3.2025.10.27.04.10.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Oct 2025 04:10:42 -0700 (PDT) Message-ID: Date: Mon, 27 Oct 2025 12:10:40 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 16/27] hw/pci-host/gpex: Allow to generate preserve boot config DSM #5 Content-Language: en-US To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, yi.l.liu@intel.com, shameerkolothum@gmail.com References: <20250929133643.38961-1-skolothumtho@nvidia.com> <20250929133643.38961-17-skolothumtho@nvidia.com> From: Eric Auger In-Reply-To: <20250929133643.38961-17-skolothumtho@nvidia.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Shameer, On 9/29/25 3:36 PM, Shameer Kolothum wrote: > From: Eric Auger > > Add a 'preserve_config' field in struct GPEXConfig and if set, generate the > DSM #5 for preserving PCI boot configurations. For SMMUV3 accel=on support, > we are making use of IORT RMRs in a subsequent patch and that requires the > DSM #5. > > At the moment the DSM generation is not yet enabled. > > Signed-off-by: Eric Auger > [Shameer: Removed possible duplicate _DSM creations] > Signed-off-by: Shameer Kolothum > Signed-off-by: Shameer Kolothum > --- > Previously, QEMU reverted an attempt to enable DSM #5 because it caused a > regression, > https://lore.kernel.org/all/20210724185234.GA2265457@roeck-us.net/. Looking at the above link again and especially the list of devices for which it was failing, it looks reasonable to me to enable that config along with accel smmu. Eric > > However, in this series, we enable it selectively, only when SMMUv3 is in > accelerator mode. The devices involved in the earlier regression are not > expected in accelerated SMMUv3 use cases. > --- > hw/pci-host/gpex-acpi.c | 29 +++++++++++++++++++++++------ > include/hw/pci-host/gpex.h | 1 + > 2 files changed, 24 insertions(+), 6 deletions(-) > > diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c > index 4587baeb78..e3825ed0b1 100644 > --- a/hw/pci-host/gpex-acpi.c > +++ b/hw/pci-host/gpex-acpi.c > @@ -51,10 +51,11 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq, > } > } > > -static Aml *build_pci_host_bridge_dsm_method(void) > +static Aml *build_pci_host_bridge_dsm_method(bool preserve_config) > { > Aml *method = aml_method("_DSM", 4, AML_NOTSERIALIZED); > Aml *UUID, *ifctx, *ifctx1, *buf; > + uint8_t byte_list[1] = {0}; > > /* PCI Firmware Specification 3.0 > * 4.6.1. _DSM for PCI Express Slot Information > @@ -64,10 +65,23 @@ static Aml *build_pci_host_bridge_dsm_method(void) > UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); > ifctx = aml_if(aml_equal(aml_arg(0), UUID)); > ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); > - uint8_t byte_list[1] = {0}; > + if (preserve_config) { > + /* support for function 0 and function 5 */ > + byte_list[0] = 0x21; > + } > buf = aml_buffer(1, byte_list); > aml_append(ifctx1, aml_return(buf)); > aml_append(ifctx, ifctx1); > + if (preserve_config) { > + Aml *ifctx2 = aml_if(aml_equal(aml_arg(2), aml_int(5))); > + /* > + * 0 - The operating system must not ignore the PCI configuration that > + * firmware has done at boot time. > + */ > + aml_append(ifctx2, aml_return(aml_int(0))); > + aml_append(ifctx, ifctx2); > + } > + > aml_append(method, ifctx); > > byte_list[0] = 0; > @@ -77,12 +91,13 @@ static Aml *build_pci_host_bridge_dsm_method(void) > } > > static void acpi_dsdt_add_host_bridge_methods(Aml *dev, > - bool enable_native_pcie_hotplug) > + bool enable_native_pcie_hotplug, > + bool preserve_config) > { > /* Declare an _OSC (OS Control Handoff) method */ > aml_append(dev, > build_pci_host_bridge_osc_method(enable_native_pcie_hotplug)); > - aml_append(dev, build_pci_host_bridge_dsm_method()); > + aml_append(dev, build_pci_host_bridge_dsm_method(preserve_config)); > } > > void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) > @@ -152,7 +167,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) > build_cxl_osc_method(dev); > } else { > /* pxb bridges do not have ACPI PCI Hot-plug enabled */ > - acpi_dsdt_add_host_bridge_methods(dev, true); > + acpi_dsdt_add_host_bridge_methods(dev, true, > + cfg->preserve_config); > } > > aml_append(scope, dev); > @@ -227,7 +243,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) > } > aml_append(dev, aml_name_decl("_CRS", rbuf)); > > - acpi_dsdt_add_host_bridge_methods(dev, cfg->pci_native_hotplug); > + acpi_dsdt_add_host_bridge_methods(dev, cfg->pci_native_hotplug, > + cfg->preserve_config); > > Aml *dev_res0 = aml_device("%s", "RES0"); > aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); > diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h > index feaf827474..7eea16e728 100644 > --- a/include/hw/pci-host/gpex.h > +++ b/include/hw/pci-host/gpex.h > @@ -46,6 +46,7 @@ struct GPEXConfig { > int irq; > PCIBus *bus; > bool pci_native_hotplug; > + bool preserve_config; > }; > > typedef struct GPEXIrq GPEXIrq;