From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
"QEMU Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v5 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime
Date: Fri, 31 Jan 2020 12:19:36 -0800 [thread overview]
Message-ID: <a7bb9abe-b364-883f-6202-a3fc5e3ee72e@linaro.org> (raw)
In-Reply-To: <CAFEAcA-FnhiRuFG49ZJ3s9OUb2VAqKtJAnceMQ8GOOyJtmHDnQ@mail.gmail.com>
On 1/31/20 5:11 AM, Peter Maydell wrote:
>> { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
>> .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
>> - .access = PL2_RW,
>> - /* no .writefn needed as this can't cause an ASID change;
>> - * no .raw_writefn or .resetfn needed as we never use mask/base_mask
>> - */
>> + .access = PL2_RW, .writefn = vmsa_tcr_el12_write,
>
> This blows away the entire TLB on a TCR_EL2 write, which is
> safe but a bit overzealous; we could skip it if E2H was clear
> (and probably also be a bit more precise about which TLB
> indexes to clear). But it's not a big deal so I'm happy if
> we leave this as-is.
Yes, it is overzealous.
I once had a patch set that attempted to track actual ASID changes and also
contained the set of tlb indexes to clear. I thought about incorporating that
here, but decided against.
r~
next prev parent reply other threads:[~2020-01-31 20:20 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-29 23:55 [PATCH v5 00/41] target/arm: Implement ARMv8.1-VHE Richard Henderson
2020-01-29 23:55 ` [PATCH v5 01/41] target/arm: Define isar_feature_aa64_vh Richard Henderson
2020-01-29 23:55 ` [PATCH v5 02/41] target/arm: Enable HCR_E2H for VHE Richard Henderson
2020-01-31 13:06 ` Peter Maydell
2020-01-31 20:13 ` Richard Henderson
2020-01-29 23:55 ` [PATCH v5 03/41] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 04/41] target/arm: Add TTBR1_EL2 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 05/41] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2020-01-29 23:55 ` [PATCH v5 06/41] target/arm: Split out vae1_tlbmask Richard Henderson
2020-01-29 23:55 ` [PATCH v5 07/41] target/arm: Split out alle1_tlbmask Richard Henderson
2020-01-29 23:55 ` [PATCH v5 08/41] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2020-01-29 23:55 ` [PATCH v5 09/41] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Richard Henderson
2020-01-29 23:55 ` [PATCH v5 10/41] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Richard Henderson
2020-01-29 23:55 ` [PATCH v5 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] Richard Henderson
2020-01-29 23:55 ` [PATCH v5 13/41] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 15/41] target/arm: Recover 4 bits from TBFLAGs Richard Henderson
2020-01-29 23:55 ` [PATCH v5 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Richard Henderson
2020-01-29 23:55 ` [PATCH v5 17/41] target/arm: Rearrange ARMMMUIdxBit Richard Henderson
2020-01-29 23:55 ` [PATCH v5 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions Richard Henderson
2020-01-29 23:55 ` [PATCH v5 19/41] target/arm: Reorganize ARMMMUIdx Richard Henderson
2020-01-29 23:55 ` [PATCH v5 20/41] target/arm: Add regime_has_2_ranges Richard Henderson
2020-01-29 23:55 ` [PATCH v5 21/41] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2020-01-29 23:55 ` [PATCH v5 22/41] target/arm: Update arm_sctlr " Richard Henderson
2020-01-29 23:55 ` [PATCH v5 23/41] target/arm: Update aa64_zva_access for EL2 Richard Henderson
2020-01-29 23:55 ` [PATCH v5 24/41] target/arm: Update ctr_el0_access " Richard Henderson
2020-01-29 23:55 ` [PATCH v5 25/41] target/arm: Add the hypervisor virtual counter Richard Henderson
2020-01-29 23:55 ` [PATCH v5 26/41] target/arm: Update timer access for VHE Richard Henderson
2020-01-29 23:56 ` [PATCH v5 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque " Richard Henderson
2020-01-29 23:56 ` [PATCH v5 28/41] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2020-01-31 13:31 ` Peter Maydell
2020-01-29 23:56 ` [PATCH v5 29/41] target/arm: Add VHE timer " Richard Henderson
2020-01-29 23:56 ` [PATCH v5 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Richard Henderson
2020-01-31 13:11 ` Peter Maydell
2020-01-31 20:19 ` Richard Henderson [this message]
2020-01-29 23:56 ` [PATCH v5 31/41] target/arm: Flush tlbs for E2&0 " Richard Henderson
2020-01-31 13:21 ` Peter Maydell
2020-01-29 23:56 ` [PATCH v5 32/41] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2020-01-29 23:56 ` [PATCH v5 33/41] target/arm: Update {fp,sve}_exception_el for VHE Richard Henderson
2020-01-29 23:56 ` [PATCH v5 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson
2020-01-29 23:56 ` [PATCH v5 35/41] target/arm: Update get_a64_user_mem_index for VHE Richard Henderson
2020-01-29 23:56 ` [PATCH v5 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 " Richard Henderson
2020-01-29 23:56 ` [PATCH v5 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2020-01-29 23:56 ` [PATCH v5 38/41] target/arm: Move arm_excp_unmasked to cpu.c Richard Henderson
2020-01-29 23:56 ` [PATCH v5 39/41] target/arm: Pass more cpu state to arm_excp_unmasked Richard Henderson
2020-01-29 23:56 ` [PATCH v5 40/41] target/arm: Use bool for unmasked in arm_excp_unmasked Richard Henderson
2020-01-29 23:56 ` [PATCH v5 41/41] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt Richard Henderson
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