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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org,
	Jackson Donaldson <jcksn@duck.com>,
	Jackson Donaldson <jackson88044@gmail.com>,
	Markus Armbruster <armbru@redhat.com>,
	"Daniel P. Berrange" <berrange@redhat.com>
Subject: Re: [PATCH] hw/misc/max78000_gcr: Do not ignore address_space_write() errors
Date: Tue, 7 Oct 2025 16:47:49 +0200	[thread overview]
Message-ID: <a7e21714-e19f-4465-96f1-dc27bd484cdf@linaro.org> (raw)
In-Reply-To: <66dbc389-4c83-4552-b447-87c0e1ada48a@linaro.org>

On 7/10/25 15:48, Philippe Mathieu-Daudé wrote:
> On 7/10/25 10:27, Peter Maydell wrote:
>> On Tue, 7 Oct 2025 at 03:40, Philippe Mathieu-Daudé 
>> <philmd@linaro.org> wrote:
>>>
>>> Convert max78000_gcr_ops[] to take MemTxAttrs and return MemTxResult,
>>> allowing the write() path to return error on failure.
>>
>> *Should* it return a MEMTX error on this failure, though?
>> This is a question of what the hardware behaviour is,
>> and there's no reference to the datasheet in this
>> commit message...
> 
> Right. Thanks!

Looking at "MAX78000 User Guide (UG7456; Rev 1; 3/2024)",
chapter "4.7.2 RAM Zeroization" and table "4-67: Memory
Zeroize Control Register", IIUC failure can not happen.

Would that change be OK?

-      address_space_write(&s->sram_as, SYSRAM0_START,
-                          MEMTXATTRS_UNSPECIFIED, zero, 0x8000);
+      /* RAM Zeroization can not fail */
+      (void)address_space_write(&s->sram_as, SYSRAM0_START,
+                                MEMTXATTRS_UNSPECIFIED, zero, 0x8000);

Otherwise, what would be the recommended way to express return value
has to be ignored? Assertion doesn't seem right, since this is not a
programming error.

Thanks,

Phil.


  reply	other threads:[~2025-10-07 14:49 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-07  2:40 [PATCH] hw/misc/max78000_gcr: Do not ignore address_space_write() errors Philippe Mathieu-Daudé
2025-10-07  8:27 ` Peter Maydell
2025-10-07 13:48   ` Philippe Mathieu-Daudé
2025-10-07 14:47     ` Philippe Mathieu-Daudé [this message]
2025-10-07 14:55       ` Peter Maydell
2025-10-07 15:25         ` Philippe Mathieu-Daudé

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