From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
To: Chen Baozi <chenbaozi@phytium.com.cn>, qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org,
Peter Maydell <peter.maydell@linaro.org>,
"open list:ARM TCG CPUs" <qemu-arm@nongnu.org>
Subject: Re: [PATCH v4] target/arm: Add Neoverse-N1 registers
Date: Mon, 13 Mar 2023 19:31:57 +0100 [thread overview]
Message-ID: <a828d259-3682-958f-1bd5-cfb571554df5@linaro.org> (raw)
In-Reply-To: <20230313033936.585669-1-chenbaozi@phytium.com.cn>
W dniu 13.03.2023 o 04:39, Chen Baozi pisze:
> Add implementation defined registers for neoverse-n1 which
> would be accessed by TF-A. Since there is no DSU in Qemu,
> CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition.
>
> Signed-off-by: Chen Baozi<chenbaozi@phytium.com.cn>
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
~ # cat /proc/cpuinfo
processor : 0
BogoMIPS : 125.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics
fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x4
CPU part : 0xd0c
CPU revision : 1
next prev parent reply other threads:[~2023-03-13 18:32 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-13 3:39 [PATCH v4] target/arm: Add Neoverse-N1 registers Chen Baozi
2023-03-13 15:17 ` Peter Maydell
2023-03-13 18:31 ` Marcin Juszkiewicz [this message]
2023-03-16 10:12 ` Peter Maydell
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