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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4255d8f4cc3sm33893324f8f.55.2025.10.09.03.00.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Oct 2025 03:00:58 -0700 (PDT) Message-ID: Date: Thu, 9 Oct 2025 12:00:58 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 7/7] target/openrisc: Replace target_ulong -> uint32_t Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= To: Anton Johansson Cc: qemu-devel@nongnu.org, Stafford Horne , Pierrick Bouvier References: <20251008075612.94193-1-philmd@linaro.org> <20251008075612.94193-8-philmd@linaro.org> <1b81d317-6c1a-42ca-8aba-7e71cfece3a5@linaro.org> In-Reply-To: <1b81d317-6c1a-42ca-8aba-7e71cfece3a5@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/10/25 10:17, Philippe Mathieu-Daudé wrote: > On 8/10/25 14:16, Anton Johansson wrote: >> On 08/10/25, Philippe Mathieu-Daudé wrote: >>> The OpenRISC targets are only built as 32-bit, therefore >>> target_ulong always expands to uint32_t. Replace and adapt >>> the API uses mechanically: >>> >>>    target_ulong -> uint32_t >>>    target_long -> int32_t >>>    tl -> i32 >>>    TCGv -> TCGv_i32 >>>    tcg_global_mem_new -> tcg_global_mem_new_i32 >>> >>> Signed-off-by: Philippe Mathieu-Daudé >>> --- >>> RFC: not sure how to split to ease review :| >>> --- >>>   target/openrisc/cpu.h        |  22 +-- >>>   target/openrisc/helper.h     |   8 +- >>>   target/openrisc/fpu_helper.c |   8 +- >>>   target/openrisc/machine.c    |  16 +- >>>   target/openrisc/sys_helper.c |   5 +- >>>   target/openrisc/translate.c  | 374 +++++++++++++++++------------------ >>>   6 files changed, 216 insertions(+), 217 deletions(-) >> >> [...] >> >>> -static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) >>> +static void gen_add(DisasContext *dc, TCGv_i32 dest, TCGv_i32 srca, >>> TCGv_i32 srcb) >>>   { >>> -    TCGv t0 = tcg_temp_new(); >>> -    TCGv res = tcg_temp_new(); >>> +    TCGv_i32 t0 = tcg_temp_new(); >>> +    TCGv_i32 res = tcg_temp_new(); >> >> I think you missed transforming tcg_temp_new -> tcg_temp_new_i32. >> >>>   static bool trans_l_lwa(DisasContext *dc, arg_load *a) >>>   { >>> -    TCGv ea; >>> +    TCGv_i32 ea; >>>       check_r0_write(dc, a->d); >>>       ea = tcg_temp_new(); >>> -    tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); >>> -    tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, MO_TEUL); >>> -    tcg_gen_mov_tl(cpu_lock_addr, ea); >>> -    tcg_gen_mov_tl(cpu_lock_value, cpu_R(dc, a->d)); >>> +    tcg_gen_addi_i32(ea, cpu_R(dc, a->a), a->i); >>> +    tcg_gen_qemu_ld_i32(cpu_R(dc, a->d), ea, dc->mem_idx, MO_TEUL); >>> +    tcg_gen_mov_i32(cpu_lock_addr, ea); >>> +    tcg_gen_mov_i32(cpu_lock_value, cpu_R(dc, a->d)); >>>       return true; >>>   } >> >> What about MO_TE -> MO_BE to handle MO_TE[SU][WL]? > > I thought we already had that merged... Found it in a branch from March 17 of this year, but forgot to post, thanks for the reminder!