From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MFDiW-0001kz-Oc for qemu-devel@nongnu.org; Fri, 12 Jun 2009 16:51:16 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MFDiV-0001j1-K7 for qemu-devel@nongnu.org; Fri, 12 Jun 2009 16:51:16 -0400 Received: from [199.232.76.173] (port=56677 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MFDiV-0001ig-8n for qemu-devel@nongnu.org; Fri, 12 Jun 2009 16:51:15 -0400 Received: from qw-out-1920.google.com ([74.125.92.145]:60553) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MFDiU-00035p-VG for qemu-devel@nongnu.org; Fri, 12 Jun 2009 16:51:15 -0400 Received: by qw-out-1920.google.com with SMTP id 4so1289526qwk.4 for ; Fri, 12 Jun 2009 13:51:14 -0700 (PDT) MIME-Version: 1.0 Date: Fri, 12 Jun 2009 16:51:13 -0400 Message-ID: From: Evan Goldenberg Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH] Incorrect MBAR offset for an5206 UART2 output port bit set List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The MBAR offset for the UART2 output port bit set function on the an5206 board, though unimplemented, is incorrectly defined as 0x1c8. The correct offset used by the hardware for this function is 0x1b8. This typo causes QEMU to crash whenever attempts to access use UART2 are made: qemu: fatal: Bad MBAR write offset 0x1b8 The following patch resolves this issue. diff --git a/hw/mcf5206.c b/hw/mcf5206.c index b570376..8bf11a4 100644 --- a/hw/mcf5206.c +++ b/hw/mcf5206.c @@ -341,7 +341,7 @@ static void m5206_mbar_write(m5206_mbar_state *s, uint32_t offset, case 0x170: s->uivr[0] = value; break; - case 0x178: case 0x17c: case 0x1c8: case 0x1bc: + case 0x178: case 0x17c: case 0x1b8: case 0x1bc: /* Not implemented: UART Output port bits. */ break; case 0x1b0: