From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: BALATON Zoltan <balaton@eik.bme.hu>,
qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Subject: Re: [PATCH 09/13] ppc4xx_pci: Rename QOM type name define
Date: Tue, 4 Jul 2023 10:56:07 +0200 [thread overview]
Message-ID: <a869053e-a26c-5d3f-537b-d81d31da26f1@linaro.org> (raw)
In-Reply-To: <217fab6a7ae5eca2a461b7d55fd76389954799b9.1688421085.git.balaton@eik.bme.hu>
On 4/7/23 00:02, BALATON Zoltan wrote:
> Rename the TYPE_PPC4xx_PCI_HOST_BRIDGE define and its string value to
> match each other and other similar types and to avoid confusion with
> "ppc4xx-host-bridge" type defined in same file.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ppc/ppc440_bamboo.c | 3 +--
> hw/ppc/ppc4xx_pci.c | 6 +++---
> include/hw/ppc/ppc4xx.h | 2 +-
> 3 files changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
> index f061b8cf3b..45f409c838 100644
> --- a/hw/ppc/ppc440_bamboo.c
> +++ b/hw/ppc/ppc440_bamboo.c
> @@ -205,8 +205,7 @@ static void bamboo_init(MachineState *machine)
> ppc4xx_sdram_ddr_enable(PPC4xx_SDRAM_DDR(dev));
>
> /* PCI */
> - dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
> - PPC440EP_PCI_CONFIG,
> + dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST, PPC440EP_PCI_CONFIG,
> qdev_get_gpio_in(uicdev, pci_irq_nrs[0]),
> qdev_get_gpio_in(uicdev, pci_irq_nrs[1]),
> qdev_get_gpio_in(uicdev, pci_irq_nrs[2]),
> diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c
> index 1d4a50fa7c..fbdf8266d8 100644
> --- a/hw/ppc/ppc4xx_pci.c
> +++ b/hw/ppc/ppc4xx_pci.c
> @@ -46,7 +46,7 @@ struct PCITargetMap {
> uint32_t la;
> };
>
> -OBJECT_DECLARE_SIMPLE_TYPE(PPC4xxPCIState, PPC4xx_PCI_HOST_BRIDGE)
> +OBJECT_DECLARE_SIMPLE_TYPE(PPC4xxPCIState, PPC4xx_PCI_HOST)
>
> #define PPC4xx_PCI_NR_PMMS 3
> #define PPC4xx_PCI_NR_PTMS 2
> @@ -321,7 +321,7 @@ static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp)
> int i;
>
> h = PCI_HOST_BRIDGE(dev);
> - s = PPC4xx_PCI_HOST_BRIDGE(dev);
> + s = PPC4xx_PCI_HOST(dev);
>
> for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
> sysbus_init_irq(sbd, &s->irq[i]);
> @@ -386,7 +386,7 @@ static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
> }
>
> static const TypeInfo ppc4xx_pcihost_info = {
> - .name = TYPE_PPC4xx_PCI_HOST_BRIDGE,
> + .name = TYPE_PPC4xx_PCI_HOST,
> .parent = TYPE_PCI_HOST_BRIDGE,
> .instance_size = sizeof(PPC4xxPCIState),
> .class_init = ppc4xx_pcihost_class_init,
> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
> index 39ca602442..e053b9751b 100644
> --- a/include/hw/ppc/ppc4xx.h
> +++ b/include/hw/ppc/ppc4xx.h
> @@ -29,7 +29,7 @@
> #include "exec/memory.h"
> #include "hw/sysbus.h"
>
> -#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
> +#define TYPE_PPC4xx_PCI_HOST "ppc4xx-pci-host"
This is the host bridge however... Maybe we want to rename:
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pci-hostbridge"
next prev parent reply other threads:[~2023-07-04 8:56 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-03 22:02 [PATCH 00/13] PPC440 devices misc clean up BALATON Zoltan
2023-07-03 22:02 ` [PATCH 01/13] ppc440: Change ppc460ex_pcie_init() parameter type BALATON Zoltan
2023-07-04 8:48 ` Philippe Mathieu-Daudé
2023-07-03 22:02 ` [PATCH 02/13] ppc440: Add cpu link property to PCIe controller model BALATON Zoltan
2023-07-04 8:46 ` Philippe Mathieu-Daudé
2023-07-03 22:02 ` [PATCH 03/13] ppc440: Add a macro to shorten PCIe controller DCR registration BALATON Zoltan
2023-07-04 8:49 ` Philippe Mathieu-Daudé
2023-07-04 9:33 ` BALATON Zoltan
2023-07-04 9:55 ` Philippe Mathieu-Daudé
2023-07-03 22:02 ` [PATCH 04/13] ppc440: Rename local variable in dcr_read_pcie() BALATON Zoltan
2023-07-04 8:50 ` Philippe Mathieu-Daudé
2023-07-03 22:02 ` [PATCH 05/13] ppc440: Stop using system io region for PCIe buses BALATON Zoltan
2023-07-04 8:51 ` Philippe Mathieu-Daudé
2023-07-04 9:48 ` BALATON Zoltan
2023-07-03 22:02 ` [PATCH 06/13] sam460ex: Remove address_space_mem local variable BALATON Zoltan
2023-07-03 22:02 ` [PATCH 07/13] ppc440: Add busnum property to PCIe controller model BALATON Zoltan
2023-07-04 8:52 ` Philippe Mathieu-Daudé
2023-07-03 22:02 ` [PATCH 08/13] ppc440: Remove ppc460ex_pcie_init legacy init function BALATON Zoltan
2023-07-04 8:53 ` Philippe Mathieu-Daudé
2023-07-03 22:02 ` [PATCH 09/13] ppc4xx_pci: Rename QOM type name define BALATON Zoltan
2023-07-04 8:56 ` Philippe Mathieu-Daudé [this message]
2023-07-03 22:02 ` [PATCH 10/13] ppc4xx_pci: Add define for ppc4xx-host-bridge type name BALATON Zoltan
2023-07-04 8:57 ` Philippe Mathieu-Daudé
2023-07-04 9:36 ` BALATON Zoltan
2023-07-03 22:02 ` [PATCH 11/13] ppc440_pcix: Rename QOM type define abd move it to common header BALATON Zoltan
2023-07-04 8:58 ` Philippe Mathieu-Daudé
2023-07-03 22:02 ` [PATCH 12/13] ppc440_pcix: Don't use iomem for regs BALATON Zoltan
2023-07-04 8:59 ` Philippe Mathieu-Daudé
2023-07-04 9:37 ` BALATON Zoltan
2023-07-04 9:57 ` Philippe Mathieu-Daudé
2023-07-04 10:14 ` BALATON Zoltan
2023-07-03 22:02 ` [PATCH 13/13] ppc440_pcix: Stop using system io region for PCI bus BALATON Zoltan
2023-07-04 9:01 ` Philippe Mathieu-Daudé
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