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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1fe524ccsm142287535e9.0.2025.03.18.11.50.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Mar 2025 11:50:37 -0700 (PDT) Message-ID: Date: Tue, 18 Mar 2025 19:50:36 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 09/13] target/arm/cpu: define ARM_MAX_VQ once for aarch32 and aarch64 To: Pierrick Bouvier , qemu-devel@nongnu.org Cc: =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= , qemu-arm@nongnu.org, alex.bennee@linaro.org, Peter Maydell , kvm@vger.kernel.org, Paolo Bonzini , Richard Henderson , =?UTF-8?Q?Marc-Andr=C3=A9_Lureau?= References: <20250318045125.759259-1-pierrick.bouvier@linaro.org> <20250318045125.759259-10-pierrick.bouvier@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250318045125.759259-10-pierrick.bouvier@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 18/3/25 05:51, Pierrick Bouvier wrote: > This will affect zregs field for aarch32. > This field is used for MVE and SVE implementations. MVE implementation > is clipping index value to 0 or 1 for zregs[*].d[], > so we should not touch the rest of data in this case anyway. We should describe why it is safe for migration. I.e. vmstate_za depends on za_needed() -> SME, not included in 32-bit cpus, etc. Should we update target/arm/machine.c in this same patch, or a preliminary one? > > Signed-off-by: Pierrick Bouvier > --- > target/arm/cpu.h | 6 +----- > 1 file changed, 1 insertion(+), 5 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 27a0d4550f2..00f78d64bd8 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -169,11 +169,7 @@ typedef struct ARMGenericTimer { > * Align the data for use with TCG host vector operations. > */ > > -#ifdef TARGET_AARCH64 > -# define ARM_MAX_VQ 16 > -#else > -# define ARM_MAX_VQ 1 > -#endif > +#define ARM_MAX_VQ 16 > > typedef struct ARMVectorReg { > uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);