From: Richard Henderson <richard.henderson@linaro.org>
To: Rebecca Cran <rebecca@nuviainc.com>,
Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v8 1/4] accel/tcg: Add TLB invalidation support for ranges of addresses
Date: Sat, 8 May 2021 08:55:45 -0700 [thread overview]
Message-ID: <a8cd4710-3de8-15c2-2f2e-3ce273639307@linaro.org> (raw)
In-Reply-To: <20210505030443.25310-2-rebecca@nuviainc.com>
On 5/4/21 8:04 PM, Rebecca Cran wrote:
> Add functions to support the FEAT_TLBIRANGE ARMv8.4 feature that adds
> TLB invalidation instructions to invalidate ranges of addresses.
>
> Signed-off-by: Rebecca Cran<rebecca@nuviainc.com>
> ---
> accel/tcg/cputlb.c | 128 +++++++++++++++++++-
> include/exec/exec-all.h | 46 +++++++
> 2 files changed, 171 insertions(+), 3 deletions(-)
I guess this is ok.
I would have switched things around such that tlb_flush_page_bits_locked used
tlb_flush_range_locked, passing TARGET_PAGE_SIZE for the length.
I would check for a very long length and flush the whole tlb, lest we spend too
long going round and round the same set of tlb entries.
I would not skip the third function in the triple, *_all_cpus, which is unused
by arm but we have for every other tlb flushing function in this set.
I'll whip something up and post it.
r~
next prev parent reply other threads:[~2021-05-08 15:57 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-05 3:04 [PATCH v8 0/4] aarch64: add support for FEAT_TLBIRANGE and FEAT_TLBIOS Rebecca Cran
2021-05-05 3:04 ` [PATCH v8 1/4] accel/tcg: Add TLB invalidation support for ranges of addresses Rebecca Cran
2021-05-08 15:55 ` Richard Henderson [this message]
2021-05-05 3:04 ` [PATCH v8 2/4] target/arm: Add support for FEAT_TLBIRANGE Rebecca Cran
2021-05-08 16:39 ` Richard Henderson
2021-05-05 3:04 ` [PATCH v8 3/4] target/arm: Add support for FEAT_TLBIOS Rebecca Cran
2021-05-08 16:46 ` Richard Henderson
2021-05-05 3:04 ` [PATCH v8 4/4] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type Rebecca Cran
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