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Sat, 08 May 2021 08:55:48 -0700 (PDT) Received: from [192.168.1.11] ([71.212.144.24]) by smtp.gmail.com with ESMTPSA id q11sm7135024pjq.6.2021.05.08.08.55.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 08 May 2021 08:55:47 -0700 (PDT) Subject: Re: [PATCH v8 1/4] accel/tcg: Add TLB invalidation support for ranges of addresses To: Rebecca Cran , Peter Maydell References: <20210505030443.25310-1-rebecca@nuviainc.com> <20210505030443.25310-2-rebecca@nuviainc.com> From: Richard Henderson Message-ID: Date: Sat, 8 May 2021 08:55:45 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: <20210505030443.25310-2-rebecca@nuviainc.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/4/21 8:04 PM, Rebecca Cran wrote: > Add functions to support the FEAT_TLBIRANGE ARMv8.4 feature that adds > TLB invalidation instructions to invalidate ranges of addresses. > > Signed-off-by: Rebecca Cran > --- > accel/tcg/cputlb.c | 128 +++++++++++++++++++- > include/exec/exec-all.h | 46 +++++++ > 2 files changed, 171 insertions(+), 3 deletions(-) I guess this is ok. I would have switched things around such that tlb_flush_page_bits_locked used tlb_flush_range_locked, passing TARGET_PAGE_SIZE for the length. I would check for a very long length and flush the whole tlb, lest we spend too long going round and round the same set of tlb entries. I would not skip the third function in the triple, *_all_cpus, which is unused by arm but we have for every other tlb flushing function in this set. I'll whip something up and post it. r~