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Thu, 15 May 2025 15:41:09 +0000 (GMT) Message-ID: Subject: Re: [PATCH 07/50] ppc/xive2: Reset Generation Flipped bit on END Cache Watch From: Miles Glenn To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, =?ISO-8859-1?Q?Fr=E9d=E9ric?= Barrat , Michael Kowal , Caleb Schlossin Date: Thu, 15 May 2025 10:41:09 -0500 In-Reply-To: <20250512031100.439842-8-npiggin@gmail.com> References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-8-npiggin@gmail.com> Organization: IBM Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-27.el8_10) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: -2qw1m5wWPGJomI4zsSJiv6IUBaaU6CI X-Authority-Analysis: v=2.4 cv=XK4wSRhE c=1 sm=1 tr=0 ts=68260b18 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VnNF1IyMAAAA:8 a=u5XRYQ9GfIdERzJa8uoA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-GUID: DfvAENBixb9VOz-SzfNE6Ea9XGnU98nu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE1NSBTYWx0ZWRfX0kmkRYufV1Hg s2cJ2s5VxWlbnA79hQXfYidgItaVr24Qsc+q/XEeKMVJf9X3w7VdaZteHDbFB0L+Ej1nyNH70lg 0m7K662ET8RyzSqfJBCxEIfQfdQbGd79/QFtQUxDMfQ4czouwvp+hj7nPd418TQLNPEytPqQK9g 2gQn8DJ/jQ29A1GGcyNrPXCiZsgsaQPm84Fp8qGrtJ2seDQHrlV7CzNWYEyhP8IPZkp5dHlM6Nr dRIaB8/FmfsSnsQbnUAzJ4AvZLsoPxKYVmw1hmC0GmCMUhK7fiNrnqk79FNpB4gEBixpqPaxc8C 4j58E9mOuRHQCjoUfJ9j3m/GMlF5hNCei01RXcQkzyaDaSk2zfz8EDCTwlvMZAeOEbqNGJzkAHp Up/sh0N7DTfgNN0NnC+ZruVGmCZZWvVYOIyw1psG4cTTXuSlcNd71P5XhUYClJzabKIJCdlp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_06,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 lowpriorityscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 adultscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150155 Received-SPF: pass client-ip=148.163.156.1; envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Glenn Miles On Mon, 2025-05-12 at 13:10 +1000, Nicholas Piggin wrote: > From: Michael Kowal > > When the END Event Queue wraps the END EQ Generation bit is flipped and the > Generation Flipped bit is set to one. On a END cache Watch read operation, > the Generation Flipped bit needs to be reset. > > While debugging an error modified END not valid error messages to include > the method since all were the same. > > Signed-off-by: Michael Kowal > --- > hw/intc/pnv_xive2.c | 3 ++- > hw/intc/xive2.c | 4 ++-- > 2 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c > index 30b4ab2efe..72cdf0f20c 100644 > --- a/hw/intc/pnv_xive2.c > +++ b/hw/intc/pnv_xive2.c > @@ -1325,10 +1325,11 @@ static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset, > case VC_ENDC_WATCH3_DATA0: > /* > * Load DATA registers from cache with data requested by the > - * SPEC register > + * SPEC register. Clear gen_flipped bit in word 1. > */ > watch_engine = (offset - VC_ENDC_WATCH0_DATA0) >> 6; > pnv_xive2_end_cache_load(xive, watch_engine); > + xive->vc_regs[reg] &= ~(uint64_t)END2_W1_GEN_FLIPPED; > val = xive->vc_regs[reg]; > break; > > diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c > index 4dd04a0398..453fe37f18 100644 > --- a/hw/intc/xive2.c > +++ b/hw/intc/xive2.c > @@ -374,8 +374,8 @@ static void xive2_end_enqueue(Xive2End *end, uint32_t data) > qgen ^= 1; > end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); > > - /* TODO(PowerNV): reset GF bit on a cache watch operation */ > - end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen); > + /* Set gen flipped to 1, it gets reset on a cache watch operation */ > + end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, 1); > } > end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); > }