From: "Wen, Qian" <qian.wen@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Cc: xiaoyao.li@intel.com, zhao1.liu@intel.com,
richard.henderson@linaro.org, babu.moger@amd.com
Subject: Re: [PATCH v4 0/2] Fix overflow of the max number of IDs for logic processor and core
Date: Mon, 11 Sep 2023 13:38:02 +0800 [thread overview]
Message-ID: <a8e3163c-0161-69df-e00c-fb12b296ecc8@intel.com> (raw)
In-Reply-To: <20230829042405.932523-1-qian.wen@intel.com>
[-- Attachment #1: Type: text/plain, Size: 1272 bytes --]
Kindly ping for any comments.
Thanks,
Qian
On 8/29/2023 12:24 PM, Qian Wen wrote:
> CPUID.1.EBX[23:16]: Maximum number of addressable IDs for logical
> processors in this physical package.
> CPUID.4:EAX[31:26]: Maximum number of addressable IDs for processor cores
> in the physical package.
>
> The current qemu code doesn't limit the value written to these two fields.
> If the guest has a huge number of cores, APs (application processor) will
> fail to bring up and the wrong info will be reported.
> According to HW behavior, setting max value written to CPUID.1.EBX[23:16]
> to 255, and CPUID.4:EAX[31:26] to 63.
>
> ---
> Changes v3 -> v4:
> - Add "Reviewed-by" from Isaku and Xiaoyao.
> - Rebase to the v8.1.0.
> Changes v2 -> v3:
> - Add patch 2.
> - Revise the commit message and comment to be clearer.
> - Using MIN() for limitation.
> Changes v1 -> v2:
> - Revise the commit message and comment to more clearer.
> - Rebased to v8.1.0-rc2.
>
> Qian Wen (2):
> target/i386: Avoid cpu number overflow in legacy topology
> target/i386: Avoid overflow of the cache parameter enumerated by leaf
> 4
>
> target/i386/cpu.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> base-commit:f5fe7c17ac4e309e47e78f0f9761aebc8d2f2c81
[-- Attachment #2: Type: text/html, Size: 1716 bytes --]
prev parent reply other threads:[~2023-09-11 5:39 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-29 4:24 [PATCH v4 0/2] Fix overflow of the max number of IDs for logic processor and core Qian Wen
2023-08-29 4:24 ` [PATCH v4 1/2] target/i386: Avoid cpu number overflow in legacy topology Qian Wen
2023-08-29 4:24 ` [PATCH v4 2/2] target/i386: Avoid overflow of the cache parameter enumerated by leaf 4 Qian Wen
2023-09-11 5:38 ` Wen, Qian [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=a8e3163c-0161-69df-e00c-fb12b296ecc8@intel.com \
--to=qian.wen@intel.com \
--cc=babu.moger@amd.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=xiaoyao.li@intel.com \
--cc=zhao1.liu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).