[Qemu-devel] [PATCH 0/3] target/mips: Add emulation of three MMI instructions

[Qemu-devel] [PATCH 0/3] target/mips: Add emulation of three MMI instructions

[Mateja Marjanovic]

From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>

This series adds emulation of PCPYH, PCPYLD, and PCPYUD MMI
instructions.

Mateja Marjanovic (3):
  target/mips: Add emulation of MMI instruction PCPYH
  target/mips: Add emulation of MMI instruction PCPYLD
  target/mips: Add emulation of MMI instruction PCPYUD

 target/mips/translate.c | 199 ++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 194 insertions(+), 5 deletions(-)

-- 
2.7.4

[Qemu-devel] [PATCH 1/3] target/mips: Add emulation of MMI instruction PCPYH

[Mateja Marjanovic]

Add emulation of MMI instruction PCPYH. The emulation is implemented
using TCG front end operations directly to achieve better performance.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
 target/mips/translate.c | 115 ++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 112 insertions(+), 3 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3b17020..a3a5f9b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4362,6 +4362,7 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
     tcg_temp_free(t1);
 }
 
+#if defined(TARGET_MIPS64)
 /* Copy GPR to and from TX79 HI1/LO1 register. */
 static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
 {
@@ -4397,6 +4398,7 @@ static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
         break;
     }
 }
+#endif
 
 /* Arithmetic on HI/LO registers */
 static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
@@ -4746,6 +4748,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
     tcg_temp_free(t1);
 }
 
+#if defined(TARGET_MIPS64)
 static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
 {
     TCGv t0, t1;
@@ -4802,6 +4805,7 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
     tcg_temp_free(t0);
     tcg_temp_free(t1);
 }
+#endif
 
 static void gen_muldiv(DisasContext *ctx, uint32_t opc,
                        int acc, int rs, int rt)
@@ -24324,6 +24328,97 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
 }
 
 
+#if defined(TARGET_MIPS64)
+
+
+/*
+ *
+ *           MMI (MultiMedia Interface) ASE instructions
+ *           ===========================================
+ */
+
+/*
+ *          MMI instructions category: data communication
+ *          ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *    PCPYH    PEXCH    PEXTLB   PINTH    PPACB    PEXT5    PREVH
+ *    PCPYLD   PEXCW    PEXTLH   PINTEH   PPACH    PPAC5    PROT3W
+ *    PCPYUD   PEXCEH   PEXTLW            PPACW
+ *             PEXCEW   PEXTUB
+ *                      PEXTUB
+ *                      PEXTUB
+ */
+
+/*
+ *  PCPYH rd, rt
+ *
+ *    Parallel Copy Halfword
+ *
+ *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ *  +-----------+---------+---------+---------+---------+-----------+
+ *  |    MMI    |0 0 0 0 0|   rt    |   rd    |  PCPYH  |    MMI3   |
+ *  +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pcpyh(DisasContext *ctx)
+{
+    uint32_t pd, rt, rd;
+    uint32_t opcode;
+
+    opcode = ctx->opcode;
+
+    pd = extract32(opcode, 21, 5);
+    rt = extract32(opcode, 16, 5);
+    rd = extract32(opcode, 11, 5);
+
+    if (unlikely(pd != 0)) {
+        generate_exception_end(ctx, EXCP_RI);
+    } else if (rd == 0) {
+        /* nop */
+    } else if (rt == 0) {
+        tcg_gen_movi_i64(cpu_gpr[rt], 0);
+        tcg_gen_movi_i64(cpu_mmr[rt], 0);
+    } else {
+        TCGv_i64 t0;
+        TCGv_i64 t1;
+        TCGv_i64 t2;
+        uint64_t mask = (1ULL << 16) - 1;
+
+        t0 = tcg_temp_new();
+        t1 = tcg_temp_new();
+        t2 = tcg_temp_new();
+
+        tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+        tcg_gen_movi_i64(t1, 0);
+        tcg_gen_or_i64(t1, t0, t1);
+        tcg_gen_shli_i64(t0, t0, 16);
+        tcg_gen_or_i64(t1, t0, t1);
+        tcg_gen_shli_i64(t0, t0, 16);
+        tcg_gen_or_i64(t1, t0, t1);
+        tcg_gen_shli_i64(t0, t0, 16);
+        tcg_gen_or_i64(t1, t0, t1);
+
+        tcg_gen_andi_i64(t0, cpu_mmr[rt], mask);
+        tcg_gen_movi_i64(t2, 0);
+        tcg_gen_or_i64(t2, t0, t2);
+        tcg_gen_shli_i64(t0, t0, 16);
+        tcg_gen_or_i64(t2, t0, t2);
+        tcg_gen_shli_i64(t0, t0, 16);
+        tcg_gen_or_i64(t2, t0, t2);
+        tcg_gen_shli_i64(t0, t0, 16);
+        tcg_gen_or_i64(t2, t0, t2);
+
+        tcg_gen_mov_i64(cpu_gpr[rd], t1);
+        tcg_gen_mov_i64(cpu_mmr[rd], t2);
+
+        tcg_temp_free(t0);
+        tcg_temp_free(t1);
+        tcg_temp_free(t2);
+    }
+}
+
+#endif
+
+
 #if !defined(TARGET_MIPS64)
 
 /* MXU accumulate add/subtract 1-bit pattern 'aptn1' */
@@ -27247,6 +27342,9 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
     }
 }
 
+
+#if defined(TARGET_MIPS64)
+
 static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
 {
     uint32_t opc = MASK_MMI0(ctx->opcode);
@@ -27370,10 +27468,12 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_3_POR:        /* TODO: MMI_OPC_3_POR */
     case MMI_OPC_3_PNOR:       /* TODO: MMI_OPC_3_PNOR */
     case MMI_OPC_3_PEXCH:      /* TODO: MMI_OPC_3_PEXCH */
-    case MMI_OPC_3_PCPYH:      /* TODO: MMI_OPC_3_PCPYH */
     case MMI_OPC_3_PEXCW:      /* TODO: MMI_OPC_3_PEXCW */
         generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
         break;
+    case MMI_OPC_3_PCPYH:
+        gen_mmi_pcpyh(ctx);
+        break;
     default:
         MIPS_INVAL("TX79 MMI class MMI3");
         generate_exception_end(ctx, EXCP_RI);
@@ -27491,6 +27591,8 @@ static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx)
     gen_mmi_sq(ctx, base, rt, offset);
 }
 
+#endif
+
 static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
 {
     int rs, rt, rd, sa;
@@ -28796,10 +28898,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         decode_opc_special(env, ctx);
         break;
     case OPC_SPECIAL2:
+#if defined(TARGET_MIPS64)
         if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
             decode_mmi(env, ctx);
-#if !defined(TARGET_MIPS64)
-        } else if (ctx->insn_flags & ASE_MXU) {
+#else
+        if (ctx->insn_flags & ASE_MXU) {
             decode_opc_mxu(env, ctx);
 #endif
         } else {
@@ -28807,11 +28910,15 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         }
         break;
     case OPC_SPECIAL3:
+#if defined(TARGET_MIPS64)
         if (ctx->insn_flags & INSN_R5900) {
             decode_mmi_sq(env, ctx);    /* MMI_OPC_SQ */
         } else {
             decode_opc_special3(env, ctx);
         }
+#else
+        decode_opc_special3(env, ctx);
+#endif
         break;
     case OPC_REGIMM:
         op1 = MASK_REGIMM(ctx->opcode);
@@ -29483,7 +29590,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         break;
     case OPC_MSA: /* OPC_MDMX */
         if (ctx->insn_flags & INSN_R5900) {
+#if defined(TARGET_MIPS64)
             gen_mmi_lq(env, ctx);    /* MMI_OPC_LQ */
+#endif
         } else {
             /* MDMX: Not implemented. */
             gen_msa(env, ctx);
-- 
2.7.4

[Qemu-devel] [PATCH 2/3] target/mips: Add emulation of MMI instruction PCPYLD

[Mateja Marjanovic]

Add emulation of MMI instruction PCPYLD. The emulation is implemented
using TCG front end operations directly to achieve better performance.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
 target/mips/translate.c | 42 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index a3a5f9b..117a29c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24416,6 +24416,44 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
     }
 }
 
+/*
+ *  PCPYLD rd, rs, rt
+ *
+ *    Parallel Copy Lower Doubleword
+ *
+ *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ *  +-----------+---------+---------+---------+---------+-----------+
+ *  |    MMI    |   rs    |   rt    |   rd    | PCPYLD  |    MMI2   |
+ *  +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pcpyld(DisasContext *ctx)
+{
+    uint32_t rs, rt, rd;
+    uint32_t opcode;
+
+    opcode = ctx->opcode;
+
+    rs = extract32(opcode, 21, 5);
+    rt = extract32(opcode, 16, 5);
+    rd = extract32(opcode, 11, 5);
+
+    if (rd == 0) {
+        /* nop */
+    } else if ((rt == 0) && (rs == 0)) {
+        tcg_gen_movi_i64(cpu_gpr[rt], 0);
+        tcg_gen_movi_i64(cpu_mmr[rt], 0);
+    } else if (rt == 0) {
+        tcg_gen_movi_i64(cpu_gpr[rd], 0);
+        tcg_gen_mov_i64(cpu_mmr[rd], cpu_gpr[rs]);
+    } else if (rs == 0) {
+        tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]);
+        tcg_gen_movi_i64(cpu_mmr[rd], 0);
+    } else {
+        tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]);
+        tcg_gen_mov_i64(cpu_mmr[rd], cpu_gpr[rs]);
+    }
+}
+
 #endif
 
 
@@ -27430,7 +27468,6 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_2_PINTH:     /* TODO: MMI_OPC_2_PINTH */
     case MMI_OPC_2_PMULTW:    /* TODO: MMI_OPC_2_PMULTW */
     case MMI_OPC_2_PDIVW:     /* TODO: MMI_OPC_2_PDIVW */
-    case MMI_OPC_2_PCPYLD:    /* TODO: MMI_OPC_2_PCPYLD */
     case MMI_OPC_2_PMADDH:    /* TODO: MMI_OPC_2_PMADDH */
     case MMI_OPC_2_PHMADH:    /* TODO: MMI_OPC_2_PHMADH */
     case MMI_OPC_2_PAND:      /* TODO: MMI_OPC_2_PAND */
@@ -27445,6 +27482,9 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_2_PROT3W:    /* TODO: MMI_OPC_2_PROT3W */
         generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 */
         break;
+    case MMI_OPC_2_PCPYLD:
+        gen_mmi_pcpyld(ctx);
+        break;
     default:
         MIPS_INVAL("TX79 MMI class MMI2");
         generate_exception_end(ctx, EXCP_RI);
-- 
2.7.4

[Qemu-devel] [PATCH 3/3] target/mips: Add emulation of MMI instruction PCPYUD

[Mateja Marjanovic]

From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>

Add emulation of MMI instruction PCPYUD. The emulation is implemented
using TCG front end operations directly to achieve better performance.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
 target/mips/translate.c | 42 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 117a29c..124f766 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24454,6 +24454,44 @@ static void gen_mmi_pcpyld(DisasContext *ctx)
     }
 }
 
+/*
+ *  PCPYUD rd, rs, rt
+ *
+ *    Parallel Copy Upper Doubleword
+ *
+ *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ *  +-----------+---------+---------+---------+---------+-----------+
+ *  |    MMI    |   rs    |   rt    |   rd    | PCPYUD  |    MMI3   |
+ *  +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pcpyud(DisasContext *ctx)
+{
+    uint32_t rs, rt, rd;
+    uint32_t opcode;
+
+    opcode = ctx->opcode;
+
+    rs = extract32(opcode, 21, 5);
+    rt = extract32(opcode, 16, 5);
+    rd = extract32(opcode, 11, 5);
+
+    if (rd == 0) {
+        /* nop */
+    } else if ((rt == 0) && (rs == 0)) {
+        tcg_gen_movi_i64(cpu_gpr[rt], 0);
+        tcg_gen_movi_i64(cpu_mmr[rt], 0);
+    } else if (rt == 0) {
+        tcg_gen_movi_i64(cpu_mmr[rd], 0);
+        tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]);
+    } else if (rs == 0) {
+        tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
+        tcg_gen_movi_i64(cpu_gpr[rd], 0);
+    } else {
+        tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
+        tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]);
+    }
+}
+
 #endif
 
 
@@ -27504,7 +27542,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_3_PINTEH:     /* TODO: MMI_OPC_3_PINTEH */
     case MMI_OPC_3_PMULTUW:    /* TODO: MMI_OPC_3_PMULTUW */
     case MMI_OPC_3_PDIVUW:     /* TODO: MMI_OPC_3_PDIVUW */
-    case MMI_OPC_3_PCPYUD:     /* TODO: MMI_OPC_3_PCPYUD */
     case MMI_OPC_3_POR:        /* TODO: MMI_OPC_3_POR */
     case MMI_OPC_3_PNOR:       /* TODO: MMI_OPC_3_PNOR */
     case MMI_OPC_3_PEXCH:      /* TODO: MMI_OPC_3_PEXCH */
@@ -27514,6 +27551,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_3_PCPYH:
         gen_mmi_pcpyh(ctx);
         break;
+    case MMI_OPC_3_PCPYUD:
+        gen_mmi_pcpyud(ctx);
+        break;
     default:
         MIPS_INVAL("TX79 MMI class MMI3");
         generate_exception_end(ctx, EXCP_RI);
-- 
2.7.4

Re: [Qemu-devel] [PATCH 0/3] target/mips: Add emulation of three MMI instructions

[Aleksandar Rikalo]

> From: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>

> Subject: [PATCH 0/3] target/mips: Add emulation of three MMI instructions
>
> From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
>
> This series adds emulation of PCPYH, PCPYLD, and PCPYUD MMI
> instructions.
>
> Mateja Marjanovic (3):
>  target/mips: Add emulation of MMI instruction PCPYH
>  target/mips: Add emulation of MMI instruction PCPYLD
>  target/mips: Add emulation of MMI instruction PCPYUD
>
> target/mips/translate.c | 199 ++++++++++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 194 insertions(+), 5 deletions(-)
>

> From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
> Sent: Friday, February 22, 2019 8:26 PM
> To: qemu-devel@nongnu.org
> Cc: aurelien@aurel32.net; Aleksandar Markovic; Aleksandar Rikalo
> Subject: [PATCH v3 0/8] Misc target/mips fixes and improvements
>
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> A collection of misc target/mips fixes and improvements for
> February 2019.
>

For all the patches in this series:

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>

Aleksandar Rikalo

Re: [Qemu-devel] [PATCH 1/3] target/mips: Add emulation of MMI instruction PCPYH

[Richard Henderson]

On 2/25/19 8:10 AM, Mateja Marjanovic wrote:
> +        tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);

tcg_gen_ext16u_i64.

> +        tcg_gen_movi_i64(t1, 0);
> +        tcg_gen_or_i64(t1, t0, t1);
> +        tcg_gen_shli_i64(t0, t0, 16);
> +        tcg_gen_or_i64(t1, t0, t1);
> +        tcg_gen_shli_i64(t0, t0, 16);
> +        tcg_gen_or_i64(t1, t0, t1);
> +        tcg_gen_shli_i64(t0, t0, 16);
> +        tcg_gen_or_i64(t1, t0, t1);

Much better as

  tcg_gen_deposit(t0, t0, t0, 16, 48);
  tcg_gen_deposit(t1, t0, t0, 32, 32);


r~

Re: [Qemu-devel] [PATCH 2/3] target/mips: Add emulation of MMI instruction PCPYLD

[Richard Henderson]

On 2/25/19 8:10 AM, Mateja Marjanovic wrote:
> +    if (rd == 0) {
> +        /* nop */
> +    } else if ((rt == 0) && (rs == 0)) {
> +        tcg_gen_movi_i64(cpu_gpr[rt], 0);
> +        tcg_gen_movi_i64(cpu_mmr[rt], 0);
> +    } else if (rt == 0) {
> +        tcg_gen_movi_i64(cpu_gpr[rd], 0);
> +        tcg_gen_mov_i64(cpu_mmr[rd], cpu_gpr[rs]);
> +    } else if (rs == 0) {
> +        tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]);
> +        tcg_gen_movi_i64(cpu_mmr[rd], 0);
> +    } else {
> +        tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]);
> +        tcg_gen_mov_i64(cpu_mmr[rd], cpu_gpr[rs]);
> +    }

You should avoid multiplying the cases this way.
The same results can be had with

  if (rd != 0) {
      gen_load_gpr(cpu_gpr[rd], rt);
      gen_load_gpr(cpu_mmr[rd], rs);
  }


r~

Re: [Qemu-devel] [PATCH 3/3] target/mips: Add emulation of MMI instruction PCPYUD

[Richard Henderson]

On 2/25/19 8:10 AM, Mateja Marjanovic wrote:
> +    if (rd == 0) {
> +        /* nop */
> +    } else if ((rt == 0) && (rs == 0)) {
> +        tcg_gen_movi_i64(cpu_gpr[rt], 0);
> +        tcg_gen_movi_i64(cpu_mmr[rt], 0);
> +    } else if (rt == 0) {
> +        tcg_gen_movi_i64(cpu_mmr[rd], 0);
> +        tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]);
> +    } else if (rs == 0) {
> +        tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
> +        tcg_gen_movi_i64(cpu_gpr[rd], 0);
> +    } else {
> +        tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
> +        tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]);
> +    }

Same as patch 2.  You may have to invent gen_load_mmr.


r~