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Mon, 13 Sep 2021 05:55:19 -0700 (PDT) Received: from [192.168.1.11] ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id z33sm7743547pga.20.2021.09.13.05.55.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Sep 2021 05:55:19 -0700 (PDT) Subject: Re: [PATCH] accel/tcg: assert insn_idx will always be valid before plugin_inject_cb To: =?UTF-8?Q?Alex_Benn=c3=a9e?= References: <20210903145938.1321571-1-alex.bennee@linaro.org> <36bc7691-c0d9-9e18-dade-4d95405dcd62@linaro.org> <871r5swztj.fsf@linaro.org> From: Richard Henderson Message-ID: Date: Mon, 13 Sep 2021 05:55:17 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <871r5swztj.fsf@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.969, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/13/21 3:06 AM, Alex Bennée wrote: >> Also, existing strageness in insn_idx being incremented for non-insns? > > It shouldn't be - it's just using the presence of the memory > instrumentation as a proxy for the start of a instruction and dealing > with the slightly different start of block boundary. > >> Should it be named something else? I haven't looked at how it's >> really used in the end. > > We need the insn idx to find the registered callbacks for a given > instruction later. We could maybe embed a metadata TCGOp that could > track this for us but that might make TCG a bit more confusing as it > doesn't really need that information? We have a metadata op for marking instruction boundaries already: INDEX_op_insn_start. r~