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([2001:b07:6468:f312:5ea:12e3:40be:7add]) by smtp.gmail.com with ESMTPSA id 26sm4745325wmf.20.2019.10.26.06.39.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 26 Oct 2019 06:39:39 -0700 (PDT) Subject: Re: [PULL 00/39] Misc (mostly x86) patches for 2019-10-24 To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Peter Maydell References: <1571925835-31930-1-git-send-email-pbonzini@redhat.com> From: Paolo Bonzini Openpgp: preference=signencrypt Message-ID: Date: Sat, 26 Oct 2019 15:39:38 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 26/10/19 15:20, Philippe Mathieu-Daud=C3=A9 wrote: > On 10/25/19 1:17 PM, Paolo Bonzini wrote: >> On 25/10/19 12:46, Peter Maydell wrote: >>> >>> x86_register_ferr_irq() is defined in target/i386/fpu_helper.c, >>> which is only built if CONFIG_TCG, but the callers don't >>> seem to be similarly guarded and there's no stub fallback. >> >> Indeed, thanks.=C2=A0 I'll add an "if (tcg_enabled())" since this feat= ure is >> not supported by accelerators other than TCG. >=20 > Paolo, since the "Split timer <-> rtc" series got merged via > the trivial tree, you need to squash this fix to patch #33 > ("mc146818rtc: Include mc146818rtc_regs.h directly in > =C2=A0mc146818rtc.c") to avoid build failure: There are a couple other semantic conflicts, so I pushed again the tag. Paolo