qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Eric Auger <eric.auger@redhat.com>
To: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com,
	ddutile@redhat.com, berrange@redhat.com, imammedo@redhat.com,
	nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com,
	gustavo.romero@linaro.org, linuxarm@huawei.com,
	wangzhou1@hisilicon.com, jiangkunkun@huawei.com,
	jonathan.cameron@huawei.com, zhangfei.gao@linaro.org
Subject: Re: [PATCH v5 10/11] qtest/bios-tables-test: Add tests for legacy smmuv3 and smmuv3 device
Date: Fri, 27 Jun 2025 14:34:13 +0200	[thread overview]
Message-ID: <a9499ef5-17c2-446b-b4d3-167ede3f4f9b@redhat.com> (raw)
In-Reply-To: <20250623094230.76084-11-shameerali.kolothum.thodi@huawei.com>



On 6/23/25 11:42 AM, Shameer Kolothum wrote:
> For the legacy SMMUv3 test, the setup includes three PCIe Root Complexes,
> one of which has bypass_iommu enabled. The generated IORT table contains
> a single SMMUv3 node and a Root Complex node with three ID mappings. Two
> of these ID mappings have output references pointing to the SMMUv3 node
> and the remianing one points to ITS.
remaining
>
> For the -device arm-smmuv3,... test, the configuration also includes three
> Root Complexes, with two connected to separate SMMUv3 devices.
By the way I have never paid attention to the fact there is only 1
single IORT node despite we have 3 GPEX/PXB devices
> The resulting IORT table contains two SMMUv3 nodes and a Root Complex node
> with ID mappings of which two of the ID mappings have output references
above is a bit difficult to parse.

Suggesting:
The resulting IORT table contains 1 RC node, 2 SMMU nodes and 1 ITS node.

> pointing to two different SMMUv3 nodes and the remaining ones to ITS.
RC node features 3 ID mappings. 2 of them target the 2 SMMU nodes while
the last one targets the ITS.
a drawing might be simpler
        pcie.0 -> {SMMU0} -> {ITS}
{RC}    pcie.1 -> {SMMU1} -> {ITS}
        pcie.2            -> {ITS}
>
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
> ---
>  tests/qtest/bios-tables-test.c | 86 ++++++++++++++++++++++++++++++++++
>  1 file changed, 86 insertions(+)
>
> diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
> index 0b2bdf9d0d..1c50541b43 100644
> --- a/tests/qtest/bios-tables-test.c
> +++ b/tests/qtest/bios-tables-test.c
> @@ -2231,6 +2231,86 @@ static void test_acpi_aarch64_virt_viot(void)
>      free_test_data(&data);
>  }
>  
> +static void test_acpi_aarch64_virt_smmuv3_legacy(void)
> +{
> +    test_data data = {
> +        .machine = "virt",
> +        .arch = "aarch64",
> +        .tcg_only = true,
> +        .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
> +        .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
> +        .ram_start = 0x40000000ULL,
> +        .scan_len = 128ULL * MiB,
> +    };
> +
> +    /*
> +     * cdrom is plugged into scsi controller to avoid conflict
> +     * with pxb-pcie. See comments in test_acpi_aarch64_virt_tcg_pxb() for
> +     * details.
> +     *
> +     * The setup includes three PCIe root complexes, one of which has
> +     * bypass_iommu enabled. The generated IORT table contains a single
> +     * SMMUv3 node and a Root Complex node with three ID mappings. Two
> +     * of the ID mappings have output references pointing to the SMMUv3
> +     * node and the remaining one points to ITS.
> +     */
> +    data.variant = ".smmuv3-legacy";
> +    test_acpi_one(" -device pcie-root-port,chassis=1,id=pci.1"
> +                  " -device virtio-scsi-pci,id=scsi0,bus=pci.1"
> +                  " -drive file="
> +                  "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2,"
> +                  "if=none,media=cdrom,id=drive-scsi0-0-0-1,readonly=on"
> +                  " -device scsi-cd,bus=scsi0.0,scsi-id=0,"
> +                  "drive=drive-scsi0-0-0-1,id=scsi0-0-0-1,bootindex=1"
> +                  " -cpu cortex-a57"
> +                  " -M iommu=smmuv3"
> +                  " -device pxb-pcie,id=pcie.1,bus=pcie.0,bus_nr=0x10"
> +                  " -device pxb-pcie,id=pcie.2,bus=pcie.0,bus_nr=0x20,bypass_iommu=on",
> +                  &data);
> +    free_test_data(&data);
> +}
> +
> +static void test_acpi_aarch64_virt_smmuv3_dev(void)
> +{
> +    test_data data = {
> +        .machine = "virt",
> +        .arch = "aarch64",
> +        .tcg_only = true,
> +        .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
> +        .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
> +        .ram_start = 0x40000000ULL,
> +        .scan_len = 128ULL * MiB,
> +    };
> +
> +    /*
> +     * cdrom is plugged into scsi controller to avoid conflict
> +     * with pxb-pcie. See comments in test_acpi_aarch64_virt_tcg_pxb()
> +     * for details.
> +     *
> +     * The setup includes three PCie root complexes, two of which are
> +     * connected to separate SMMUv3 devices. The resulting IORT table
> +     * contains two SMMUv3 nodes and a Root Complex node with ID mappings
> +     * of which two of the ID mappings have output references pointing
> +     * to two different SMMUv3 nodes and the remaining ones pointing to
> +     * ITS.
> +     */
> +    data.variant = ".smmuv3-dev";
> +    test_acpi_one(" -device pcie-root-port,chassis=1,id=pci.1"
> +                  " -device virtio-scsi-pci,id=scsi0,bus=pci.1"
> +                  " -drive file="
> +                  "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2,"
> +                  "if=none,media=cdrom,id=drive-scsi0-0-0-1,readonly=on"
> +                  " -device scsi-cd,bus=scsi0.0,scsi-id=0,"
> +                  "drive=drive-scsi0-0-0-1,id=scsi0-0-0-1,bootindex=1"
> +                  " -cpu cortex-a57"
> +                  " -device arm-smmuv3,primary-bus=pcie.0,id=smmuv3.0"
> +                  " -device pxb-pcie,id=pcie.1,bus=pcie.0,bus_nr=0x10"
> +                  " -device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1"
> +                  " -device pxb-pcie,id=pcie.2,bus=pcie.0,bus_nr=0x20",
> +                  &data);
> +    free_test_data(&data);
> +}
> +
>  #ifndef _WIN32
>  # define DEV_NULL "/dev/null"
>  #else
> @@ -2586,6 +2666,12 @@ int main(int argc, char *argv[])
>              if (qtest_has_device("virtio-iommu-pci")) {
>                  qtest_add_func("acpi/virt/viot", test_acpi_aarch64_virt_viot);
>              }
> +            qtest_add_func("acpi/virt/smmuv3-legacy",
> +                           test_acpi_aarch64_virt_smmuv3_legacy);
> +            if (qtest_has_device("arm-smmuv3")) {
> +                qtest_add_func("acpi/virt/smmuv3-dev",
> +                               test_acpi_aarch64_virt_smmuv3_dev);
> +            }
>          }
>      } else if (strcmp(arch, "riscv64") == 0) {
>          if (has_tcg && qtest_has_device("virtio-blk-pci")) {
Besides
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Eric



  parent reply	other threads:[~2025-06-27 12:34 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-23  9:42 [PATCH v5 00/11] hw/arm/virt: Add support for user creatable SMMUv3 device Shameer Kolothum via
2025-06-23  9:42 ` [PATCH v5 01/11] hw/arm/smmu-common: Check SMMU has PCIe Root Complex association Shameer Kolothum via
2025-06-23 11:32   ` Jonathan Cameron via
2025-06-27 11:52   ` Eric Auger
2025-06-30  7:01     ` Shameerali Kolothum Thodi via
2025-07-01  6:31       ` Eric Auger
2025-06-23  9:42 ` [PATCH v5 02/11] hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build Shameer Kolothum via
2025-06-27 11:54   ` Eric Auger
2025-06-23  9:42 ` [PATCH v5 03/11] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices Shameer Kolothum via
2025-06-23  9:42 ` [PATCH v5 04/11] hw/arm/virt: Factor out common SMMUV3 dt bindings code Shameer Kolothum via
2025-06-23  9:42 ` [PATCH v5 05/11] hw/arm/virt: Add an SMMU_IO_LEN macro Shameer Kolothum via
2025-06-23 11:35   ` Jonathan Cameron via
2025-06-23  9:42 ` [PATCH v5 06/11] hw/pci: Introduce pci_setup_iommu_per_bus() for per-bus IOMMU ops retrieval Shameer Kolothum via
2025-06-23 11:39   ` Jonathan Cameron via
2025-06-27 12:04   ` Eric Auger
2025-06-30  7:05     ` Shameerali Kolothum Thodi via
2025-06-23  9:42 ` [PATCH v5 07/11] hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation Shameer Kolothum via
2025-06-23 11:46   ` Jonathan Cameron via
2025-06-27 12:05   ` Eric Auger
2025-06-23  9:42 ` [PATCH v5 08/11] qemu-options.hx: Document the arm-smmuv3 device Shameer Kolothum via
2025-06-23 11:47   ` Jonathan Cameron via
2025-06-27 12:08   ` Eric Auger
2025-06-23  9:42 ` [PATCH v5 09/11] bios-tables-test: Allow for smmuv3 test data Shameer Kolothum via
2025-06-23 11:49   ` Jonathan Cameron via
2025-06-27 12:14   ` Eric Auger
2025-06-23  9:42 ` [PATCH v5 10/11] qtest/bios-tables-test: Add tests for legacy smmuv3 and smmuv3 device Shameer Kolothum via
2025-06-23 11:57   ` Jonathan Cameron via
2025-06-27 12:34   ` Eric Auger [this message]
2025-06-30  7:08     ` Shameerali Kolothum Thodi via
2025-06-23  9:42 ` [PATCH v5 11/11] qtest/bios-tables-test: Update tables for smmuv3 tests Shameer Kolothum via
2025-06-23 12:00   ` Jonathan Cameron via
2025-06-27 12:36   ` Eric Auger
2025-06-30  7:11     ` Shameerali Kolothum Thodi via
2025-07-01  6:35       ` Eric Auger
2025-06-27 12:36 ` [PATCH v5 00/11] hw/arm/virt: Add support for user creatable SMMUv3 device Eric Auger
2025-06-30  7:12   ` Shameerali Kolothum Thodi via
2025-07-01  6:37     ` Eric Auger
2025-07-02  1:01 ` Nathan Chen
2025-07-02 15:08   ` Shameerali Kolothum Thodi via

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=a9499ef5-17c2-446b-b4d3-167ede3f4f9b@redhat.com \
    --to=eric.auger@redhat.com \
    --cc=berrange@redhat.com \
    --cc=ddutile@redhat.com \
    --cc=gustavo.romero@linaro.org \
    --cc=imammedo@redhat.com \
    --cc=jgg@nvidia.com \
    --cc=jiangkunkun@huawei.com \
    --cc=jonathan.cameron@huawei.com \
    --cc=linuxarm@huawei.com \
    --cc=mochs@nvidia.com \
    --cc=nathanc@nvidia.com \
    --cc=nicolinc@nvidia.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=shameerali.kolothum.thodi@huawei.com \
    --cc=smostafa@google.com \
    --cc=wangzhou1@hisilicon.com \
    --cc=zhangfei.gao@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).