* [Qemu-devel] target-alpha mttcg success
@ 2016-11-12 16:57 Richard Henderson
2016-11-13 9:39 ` Alex Bennée
0 siblings, 1 reply; 3+ messages in thread
From: Richard Henderson @ 2016-11-12 16:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Alex Bennée
> PID USER PR NI VIRT RES S P %CPU %MEM TIME+ COMMAND
> 7817 rth 20 0 5304360 712404 R 3 94.4 9.1 2:45.21 qemu-system-alp
> 7819 rth 20 0 5304360 712404 R 1 90.7 9.1 2:01.84 qemu-system-alp
> 7818 rth 20 0 5304360 712404 R 2 90.1 9.1 2:04.52 qemu-system-alp
> 7820 rth 20 0 5304360 712404 R 0 89.4 9.1 1:49.37 qemu-system-alp
> 7811 rth 20 0 5304360 712404 S 1 9.6 9.1 0:10.76 qemu-system-alp
Whee! During a guest make -j4 build of glibc.
On top of Alex's latest patch set all that is required for basic success is an
update to the alpha bios. Which until today didn't support smp at all.
There does appear to be a problem with delivery of ISA interrupts for smp,
regardless whether mttcg is enabled or not, though PCI interrupts are working
fine. This appears in that both serial console and ps2 keyboard are
non-responsive, but one can ssh into the guest. Which doesn't make a whole lot
of sense. More debugging required, I suppose.
I'll post the palcode update once the mttcg patch set is merged.
r~
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] target-alpha mttcg success
2016-11-12 16:57 [Qemu-devel] target-alpha mttcg success Richard Henderson
@ 2016-11-13 9:39 ` Alex Bennée
2016-11-13 11:03 ` Richard Henderson
0 siblings, 1 reply; 3+ messages in thread
From: Alex Bennée @ 2016-11-13 9:39 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Pranith Kumar
Richard Henderson <rth@twiddle.net> writes:
>> PID USER PR NI VIRT RES S P %CPU %MEM TIME+ COMMAND
>> 7817 rth 20 0 5304360 712404 R 3 94.4 9.1 2:45.21 qemu-system-alp
>> 7819 rth 20 0 5304360 712404 R 1 90.7 9.1 2:01.84 qemu-system-alp
>> 7818 rth 20 0 5304360 712404 R 2 90.1 9.1 2:04.52 qemu-system-alp
>> 7820 rth 20 0 5304360 712404 R 0 89.4 9.1 1:49.37 qemu-system-alp
>> 7811 rth 20 0 5304360 712404 S 1 9.6 9.1 0:10.76 qemu-system-alp
>
> Whee! During a guest make -j4 build of glibc.
\o/
>
> On top of Alex's latest patch set all that is required for basic success is an
> update to the alpha bios. Which until today didn't support smp at all.
>
> There does appear to be a problem with delivery of ISA interrupts for smp,
> regardless whether mttcg is enabled or not, though PCI interrupts are working
> fine. This appears in that both serial console and ps2 keyboard are
> non-responsive, but one can ssh into the guest. Which doesn't make a whole lot
> of sense. More debugging required, I suppose.
Hmm weird. I was helping Pranith with debugging one of his aarch64 guest
setups under TCG and it seemed to be loosing IRQs, I could see level=1
breakpoints being hit in qemu_set_irq but no delivery of the IRQ to the
CPU. Unfortunately I had to head home before we got to the bottom of it
but I wonder if it is related.
As far as the core code is concerned IRQ updates should be protected by
the BQL.
>
> I'll post the palcode update once the mttcg patch set is merged.
>
>
> r~
Good stuff ;-)
--
Alex Bennée
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] target-alpha mttcg success
2016-11-13 9:39 ` Alex Bennée
@ 2016-11-13 11:03 ` Richard Henderson
0 siblings, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2016-11-13 11:03 UTC (permalink / raw)
To: Alex Bennée; +Cc: qemu-devel, Pranith Kumar
On 11/13/2016 10:39 AM, Alex Bennée wrote:
>> There does appear to be a problem with delivery of ISA interrupts for smp,
>> regardless whether mttcg is enabled or not, though PCI interrupts are working
>> fine. This appears in that both serial console and ps2 keyboard are
>> non-responsive, but one can ssh into the guest. Which doesn't make a whole lot
>> of sense. More debugging required, I suppose.
>
> Hmm weird. I was helping Pranith with debugging one of his aarch64 guest
> setups under TCG and it seemed to be loosing IRQs, I could see level=1
> breakpoints being hit in qemu_set_irq but no delivery of the IRQ to the
> CPU. Unfortunately I had to head home before we got to the bottom of it
> but I wonder if it is related.
Interesting. Please keep me in the loop on that one.
> As far as the core code is concerned IRQ updates should be protected by
> the BQL.
Good, that confirms what I remembered on the subject.
r~
^ permalink raw reply [flat|nested] 3+ messages in thread
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2016-11-13 11:03 ` Richard Henderson
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