[PATCH 0/2] target/sparc: Enable MTTCG

[PATCH 0/2] target/sparc: Enable MTTCG

[Richard Henderson]

With the addition of TCG_GUEST_DEFAULT_MO, there's nothing in
the cpu emulation preventing this from working.  There is some
board model work to be done for sparc64, where max_cpus = 1.


r~


Richard Henderson (2):
  target/sparc: Set TCG_GUEST_DEFAULT_MO
  configs: Enable MTTCG for sparc, sparc64

 configs/targets/sparc-softmmu.mak   |  1 +
 configs/targets/sparc64-softmmu.mak |  1 +
 target/sparc/cpu.h                  | 23 +++++++++++++++++++++++
 3 files changed, 25 insertions(+)

-- 
2.34.1

[PATCH 1/2] target/sparc: Set TCG_GUEST_DEFAULT_MO

[Richard Henderson]

Always use TSO, per the Oracle 2015 manual.
This is slightly less restrictive than the TCG_MO_ALL default,
and happens to match the i386 model, which will eliminate a few
extra barriers on that host.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/cpu.h | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 3d090e8278..49c53f5c40 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -6,6 +6,29 @@
 #include "exec/cpu-defs.h"
 #include "qemu/cpu-float.h"
 
+/*
+ * From Oracle SPARC Architecture 2015:
+ *
+ *   Compatibility notes: The PSO memory model described in SPARC V8 and
+ *   SPARC V9 compatibility architecture specifications was never implemented
+ *   in a SPARC V9 implementation and is not included in the Oracle SPARC
+ *   Architecture specification.
+ *
+ *   The RMO memory model described in the SPARC V9 specification was
+ *   implemented in some non-Sun SPARC V9 implementations, but is not
+ *   directly supported in Oracle SPARC Architecture 2015 implementations.
+ *
+ * Therefore always use TSO in QEMU.
+ *
+ * D.5 Specification of Partial Store Order (PSO)
+ *   ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
+ *
+ * D.6 Specification of Total Store Order (TSO)
+ *   ... PSO with the additional requirement that all [stores] are followed
+ *   by an implied MEMBAR #StoreStore.
+ */
+#define TCG_GUEST_DEFAULT_MO  (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST)
+
 #if !defined(TARGET_SPARC64)
 #define TARGET_DPREGS 16
 #else
-- 
2.34.1

Re: [PATCH 1/2] target/sparc: Set TCG_GUEST_DEFAULT_MO

[Philippe Mathieu-Daudé]

On 20/6/23 18:40, Richard Henderson wrote:
> Always use TSO, per the Oracle 2015 manual.
> This is slightly less restrictive than the TCG_MO_ALL default,
> and happens to match the i386 model, which will eliminate a few
> extra barriers on that host.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/sparc/cpu.h | 23 +++++++++++++++++++++++
>   1 file changed, 23 insertions(+)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

[PATCH 2/2] configs: Enable MTTCG for sparc, sparc64

[Richard Henderson]

This will be of small comfort to sparc64, because both
sun4u and sun4v board models force max_cpus = 1.
But it does enable actual smp for sparc32 sun4m.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 configs/targets/sparc-softmmu.mak   | 1 +
 configs/targets/sparc64-softmmu.mak | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak
index 454eb35499..a5d9200382 100644
--- a/configs/targets/sparc-softmmu.mak
+++ b/configs/targets/sparc-softmmu.mak
@@ -1,2 +1,3 @@
 TARGET_ARCH=sparc
 TARGET_BIG_ENDIAN=y
+TARGET_SUPPORTS_MTTCG=y
diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak
index d3f8a3b710..36ca64ec41 100644
--- a/configs/targets/sparc64-softmmu.mak
+++ b/configs/targets/sparc64-softmmu.mak
@@ -1,3 +1,4 @@
 TARGET_ARCH=sparc64
 TARGET_BASE_ARCH=sparc
 TARGET_BIG_ENDIAN=y
+TARGET_SUPPORTS_MTTCG=y
-- 
2.34.1

Re: [PATCH 2/2] configs: Enable MTTCG for sparc, sparc64

[Philippe Mathieu-Daudé]

On 20/6/23 18:40, Richard Henderson wrote:
> This will be of small comfort to sparc64, because both
> sun4u and sun4v board models force max_cpus = 1.
> But it does enable actual smp for sparc32 sun4m.

Yay \o/

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   configs/targets/sparc-softmmu.mak   | 1 +
>   configs/targets/sparc64-softmmu.mak | 1 +
>   2 files changed, 2 insertions(+)

Re: [PATCH 0/2] target/sparc: Enable MTTCG

[Mark Cave-Ayland]

On 20/06/2023 17:40, Richard Henderson wrote:

> With the addition of TCG_GUEST_DEFAULT_MO, there's nothing in
> the cpu emulation preventing this from working.  There is some
> board model work to be done for sparc64, where max_cpus = 1.

I've tried testing this with the Advent Calendar image at 
https://qemu-advent-calendar.org/2018/download/day11.tar.xz and even without these 
patches applied I'm seeing hangs with -smp 2. When applied on top of the other 
"target/sparc: Use tcg_gen_lookup_and_goto_ptr" series I get assert() after a minute 
or two:

ERROR:../accel/tcg/tcg-accel-ops-mttcg.c:110:mttcg_cpu_thread_fn: assertion failed: 
(cpu->halted)
Bail out! ERROR:../accel/tcg/tcg-accel-ops-mttcg.c:110:mttcg_cpu_thread_fn: assertion 
failed: (cpu->halted)

It may be wise to try and figure out what's going on with git head first before 
applying this. In particular /proc/cpuinfo suggests things aren't right with -smp 2:

# cat /proc/cpuinfo
cpu             : Texas Instruments, Inc. - SuperSparc-(II)
fpu             : SuperSparc on-chip FPU
promlib         : Version 3 Revision 2
prom            : 2.25
type            : sun4m
ncpus probed    : 2
ncpus active    : 1
CPU0Bogo        : 213.50
CPU0ClkTck      : 0
MMU type        : TI Viking/MXCC
contexts        : 65536
nocache total   : 3145728
nocache used    : 375552

> Richard Henderson (2):
>    target/sparc: Set TCG_GUEST_DEFAULT_MO
>    configs: Enable MTTCG for sparc, sparc64
> 
>   configs/targets/sparc-softmmu.mak   |  1 +
>   configs/targets/sparc64-softmmu.mak |  1 +
>   target/sparc/cpu.h                  | 23 +++++++++++++++++++++++
>   3 files changed, 25 insertions(+)


ATB,

Mark.

Re: [PATCH 0/2] target/sparc: Enable MTTCG

[Richard Henderson]

On 6/22/23 16:36, Mark Cave-Ayland wrote:
> On 20/06/2023 17:40, Richard Henderson wrote:
> 
>> With the addition of TCG_GUEST_DEFAULT_MO, there's nothing in
>> the cpu emulation preventing this from working.  There is some
>> board model work to be done for sparc64, where max_cpus = 1.
> 
> I've tried testing this with the Advent Calendar image at 
> https://qemu-advent-calendar.org/2018/download/day11.tar.xz and even without these patches 
> applied I'm seeing hangs with -smp 2. When applied on top of the other "target/sparc: Use 
> tcg_gen_lookup_and_goto_ptr" series I get assert() after a minute or two:

Would you try again, now that we've solved the issues with lookup_and_goto_ptr?


r~

Re: [PATCH 0/2] target/sparc: Enable MTTCG

[Mark Cave-Ayland]

On 30/06/2023 19:05, Richard Henderson wrote:

> On 6/22/23 16:36, Mark Cave-Ayland wrote:
>> On 20/06/2023 17:40, Richard Henderson wrote:
>>
>>> With the addition of TCG_GUEST_DEFAULT_MO, there's nothing in
>>> the cpu emulation preventing this from working.  There is some
>>> board model work to be done for sparc64, where max_cpus = 1.
>>
>> I've tried testing this with the Advent Calendar image at 
>> https://qemu-advent-calendar.org/2018/download/day11.tar.xz and even without these 
>> patches applied I'm seeing hangs with -smp 2. When applied on top of the other 
>> "target/sparc: Use tcg_gen_lookup_and_goto_ptr" series I get assert() after a 
>> minute or two:
> 
> Would you try again, now that we've solved the issues with lookup_and_goto_ptr?

The wording above is a bit clumsy on my part, but I was still seeing the hangs on git 
master with -smp 2, but with the older tcg_gen_lookup_and_goto_ptr series not only 
would I see the hangs but I would hit the assert() within a couple of minutes.

My notes on the wiki at https://wiki.qemu.org/Documentation/Platforms/SPARC#Timeline 
suggest that it was working on QEMU 6.2, so I'll need to find a moment to bisect it 
down to see where things broke.


ATB,

Mark.