From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair23@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
"Frank Chang" <frank.chang@sifive.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Fabien Portas" <fabien.portas@grenoble-inp.org>,
"Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
liuzhiwei <zhiwei_liu@c-sky.com>
Subject: Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand
Date: Sun, 17 Oct 2021 22:31:53 -0700 [thread overview]
Message-ID: <a9a1b623-0420-6285-0ad8-cf152a4e0397@linaro.org> (raw)
In-Reply-To: <CAKmqyKOZd-gtes+_sQ=ndjqu9nfujE_Kc==Jueno+ds6Pg7neQ@mail.gmail.com>
On 10/17/21 9:52 PM, Alistair Francis wrote:
> On Sun, Oct 17, 2021 at 3:32 AM Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> The position of this read-only field is dependent on the
>> current cpu width. Rather than having to compute that
>> difference in many places, compute it only on read.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>
> This means that the value reported by riscv_cpu_dump_state() and GDB
> will both be incorrect though?
Yep. Missed those; should have added another accessor.
Also, for the record, it changes the vmstate, but since a previous patch in the series
bumped the version number for the split on misa, we can call all of a piece and ok.
r~
next prev parent reply other threads:[~2021-10-18 5:33 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-16 17:13 [PATCH v3 00/14] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-16 17:13 ` [PATCH v3 01/14] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-16 17:14 ` [PATCH v3 02/14] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-16 17:14 ` [PATCH v3 03/14] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-18 11:46 ` LIU Zhiwei
2021-10-16 17:14 ` [PATCH v3 04/14] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-18 11:51 ` LIU Zhiwei
2021-10-16 17:14 ` [PATCH v3 05/14] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-18 11:55 ` LIU Zhiwei
2021-10-16 17:14 ` [PATCH v3 06/14] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-16 17:14 ` [PATCH v3 07/14] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-16 17:14 ` [PATCH v3 08/14] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-16 17:14 ` [PATCH v3 09/14] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-16 17:14 ` [PATCH v3 10/14] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-18 4:36 ` Alistair Francis
2021-10-16 17:14 ` [PATCH v3 11/14] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-16 17:14 ` [PATCH v3 12/14] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-18 4:37 ` Alistair Francis
2021-10-16 17:14 ` [PATCH v3 13/14] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
2021-10-18 4:43 ` Alistair Francis
2021-10-16 17:14 ` [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand Richard Henderson
2021-10-18 4:52 ` Alistair Francis
2021-10-18 5:31 ` Richard Henderson [this message]
2021-10-18 5:38 ` Alistair Francis
2021-10-18 6:05 ` Richard Henderson
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