From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com
Subject: Re: [PATCH 05/13] target/riscv: Calculate address according to ol
Date: Mon, 1 Nov 2021 23:56:02 +0800 [thread overview]
Message-ID: <a9b16bdb-a998-1a81-26c1-b3411b988f01@c-sky.com> (raw)
In-Reply-To: <a6ceb4fb-6a29-066b-23dd-114494d19e59@linaro.org>
On 2021/11/1 下午6:46, Richard Henderson wrote:
> On 11/1/21 6:01 AM, LIU Zhiwei wrote:
>> static bool trans_fld(DisasContext *ctx, arg_fld *a)
>> {
>> - TCGv addr;
>> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
>> + TCGv addr = temp_new(ctx);
>> REQUIRE_FPU;
>> REQUIRE_EXT(ctx, RVD);
>> - addr = get_gpr(ctx, a->rs1, EXT_NONE);
>> - if (a->imm) {
>> - TCGv temp = temp_new(ctx);
>> - tcg_gen_addi_tl(temp, addr, a->imm);
>> - addr = temp;
>> - }
>> + tcg_gen_addi_tl(addr, src1, a->imm);
>> addr = gen_pm_adjust_address(ctx, addr);
>
> No change here,
Oops, an error here.
>
>> static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
>> {
>> - TCGv addr;
>> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
>> + TCGv addr = temp_new(ctx);
>> REQUIRE_FPU;
>> REQUIRE_EXT(ctx, RVD);
>> - addr = get_gpr(ctx, a->rs1, EXT_NONE);
>> - if (a->imm) {
>> - TCGv temp = temp_new(ctx);
>> - tcg_gen_addi_tl(temp, addr, a->imm);
>> - addr = temp;
>> - }
>> + tcg_gen_addi_tl(addr, src1, a->imm);
>> addr = gen_pm_adjust_address(ctx, addr);
>
> Or here.
The same error.
>
>> static bool trans_flw(DisasContext *ctx, arg_flw *a)
>> {
>> TCGv_i64 dest;
>> - TCGv addr;
>> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
>> + TCGv addr = temp_new(ctx);
>> REQUIRE_FPU;
>> REQUIRE_EXT(ctx, RVF);
>> - addr = get_gpr(ctx, a->rs1, EXT_NONE);
>> - if (a->imm) {
>> - TCGv temp = temp_new(ctx);
>> - tcg_gen_addi_tl(temp, addr, a->imm);
>> - addr = temp;
>> + tcg_gen_addi_tl(addr, src1, a->imm);
>> + if (ctx->ol == MXL_RV32) {
>> + tcg_gen_ext32u_tl(addr, addr);
>> }
>> addr = gen_pm_adjust_address(ctx, addr);
>
> But you did here.
That's what I want to.
>
> (1) OL is wrong, use XL.
OK.
>
> (2) The address adjustment should be done in some common routine.
> Probably rename gen_pm_adjust_address to make it more generic,
> then add the XL truncation there.
Yes, the XL truncation should be placed after gen_pm_adjust_address.
Maybe we can define a common routine to get address, and in the common
routine
we calculate the address and adjust it with pointer mask and xl.
Thanks,
Zhiwei
>
>
> r~
next prev parent reply other threads:[~2021-11-01 15:57 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-01 10:01 [PATCH 00/13] Support UXL filed in xstatus LIU Zhiwei
2021-11-01 10:01 ` [PATCH 01/13] target/riscv: Sign extend pc for different ol LIU Zhiwei
2021-11-01 10:29 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 02/13] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-01 10:33 ` Richard Henderson
2021-11-02 1:48 ` LIU Zhiwei
2021-11-02 10:18 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 03/13] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-01 10:35 ` Richard Henderson
2021-11-02 10:20 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 04/13] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-01 10:40 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 05/13] target/riscv: Calculate address according to ol LIU Zhiwei
2021-11-01 10:46 ` Richard Henderson
2021-11-01 15:56 ` LIU Zhiwei [this message]
2021-11-01 10:01 ` [PATCH 06/13] target/riscv: Adjust vsetvl " LIU Zhiwei
2021-11-01 10:53 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 07/13] target/riscv: Ajdust vector atomic check with ol LIU Zhiwei
2021-11-01 10:55 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 08/13] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-01 13:41 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 09/13] target/riscv: Adjust vector address with ol LIU Zhiwei
2021-11-01 11:35 ` Richard Henderson
2021-11-08 9:28 ` LIU Zhiwei
2021-11-09 6:37 ` Richard Henderson
2021-11-09 8:04 ` LIU Zhiwei
2021-11-09 8:18 ` Richard Henderson
2021-11-09 8:39 ` LIU Zhiwei
2021-11-09 9:05 ` LIU Zhiwei
2021-11-09 9:25 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 10/13] target/riscv: Adjust scalar reg in vector " LIU Zhiwei
2021-11-01 16:33 ` Richard Henderson
2021-11-08 9:38 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 11/13] target/riscv: Switch context in exception return LIU Zhiwei
2021-11-01 16:43 ` Richard Henderson
2021-11-08 11:23 ` LIU Zhiwei
2021-11-09 6:38 ` LIU Zhiwei
2021-11-09 6:51 ` LIU Zhiwei
2021-11-01 10:01 ` [PATCH 12/13] target/riscv: Don't save pc when " LIU Zhiwei
2021-11-01 16:49 ` Richard Henderson
2021-11-01 10:01 ` [PATCH 13/13] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-01 17:01 ` Richard Henderson
2021-11-08 12:10 ` LIU Zhiwei
2021-11-10 3:01 ` LIU Zhiwei
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