Re: [PATCH] target/riscv: Flush the TLB entry for the specified address

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

Hi,

On 30/9/25 11:48, wang.yechao255@zte.com.cn wrote:
> From: yechao-w <wang.yechao255@zte.com.cn>
> 
> When the guest executes sfence/svinval with an address parameter,
> invalidating only the specific TLB entry for that address rather
> than the entire TLB enhances TCG performance.
> 
> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>
> ---
>   target/riscv/helper.h                          | 2 +-
>   target/riscv/insn_trans/trans_privileged.c.inc | 4 +++-
>   target/riscv/insn_trans/trans_svinval.c.inc    | 4 +++-
>   target/riscv/op_helper.c                       | 8 ++++++--
>   4 files changed, 13 insertions(+), 5 deletions(-)


> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 110292e84d..0fe5fcb3ac 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -555,7 +555,7 @@ void helper_wrs_nto(CPURISCVState *env)
>       }
>   }
> 
> -void helper_tlb_flush(CPURISCVState *env)
> +void helper_tlb_flush(CPURISCVState *env, target_ulong addr)
>   {
>       CPUState *cs = env_cpu(env);
>       if (!env->virt_enabled &&
> @@ -566,7 +566,11 @@ void helper_tlb_flush(CPURISCVState *env)
>                  (env->priv == PRV_U || get_field(env->hstatus, HSTATUS_VTVM))) {
>           riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
>       } else {
> -        tlb_flush(cs);
> +        if (addr) {
> +            tlb_flush_page(cs, addr);

I suspect tlb_flush_page(cs, addr) is the right thing to do,
even for addr=0.

Can you point at the doc?

> +        } else {
> +            tlb_flush(cs);
> +        }
>       }
>   }
>