[PATCH] target/riscv: Flush the TLB entry for the specified address

[PATCH] target/riscv: Flush the TLB entry for the specified address

[wang.yechao255]

From: yechao-w <wang.yechao255@zte.com.cn>

When the guest executes sfence/svinval with an address parameter,
invalidating only the specific TLB entry for that address rather
than the entire TLB enhances TCG performance.

Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>
---
 target/riscv/helper.h                          | 2 +-
 target/riscv/insn_trans/trans_privileged.c.inc | 4 +++-
 target/riscv/insn_trans/trans_svinval.c.inc    | 4 +++-
 target/riscv/op_helper.c                       | 8 ++++++--
 4 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f712b1c368..de3757fa75 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -135,7 +135,7 @@ DEF_HELPER_1(mnret, tl, env)
 DEF_HELPER_1(ctr_clear, void, env)
 DEF_HELPER_1(wfi, void, env)
 DEF_HELPER_1(wrs_nto, void, env)
-DEF_HELPER_1(tlb_flush, void, env)
+DEF_HELPER_2(tlb_flush, void, env, tl)
 DEF_HELPER_1(tlb_flush_all, void, env)
 DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl)
 /* Native Debug */
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 8a62b4cfcd..b6865f51b2 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -154,8 +154,10 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
 static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
 {
 #ifndef CONFIG_USER_ONLY
+    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+
     decode_save_opc(ctx, 0);
-    gen_helper_tlb_flush(tcg_env);
+    gen_helper_tlb_flush(tcg_env, addr);
     return true;
 #endif
     return false;
diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
index a06c3b214f..1b1b932ac6 100644
--- a/target/riscv/insn_trans/trans_svinval.c.inc
+++ b/target/riscv/insn_trans/trans_svinval.c.inc
@@ -24,12 +24,14 @@

 static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
 {
+    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+
     REQUIRE_SVINVAL(ctx);
     /* Do the same as sfence.vma currently */
     REQUIRE_EXT(ctx, RVS);
 #ifndef CONFIG_USER_ONLY
     decode_save_opc(ctx, 0);
-    gen_helper_tlb_flush(tcg_env);
+    gen_helper_tlb_flush(tcg_env, addr);
     return true;
 #endif
     return false;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 110292e84d..0fe5fcb3ac 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -555,7 +555,7 @@ void helper_wrs_nto(CPURISCVState *env)
     }
 }

-void helper_tlb_flush(CPURISCVState *env)
+void helper_tlb_flush(CPURISCVState *env, target_ulong addr)
 {
     CPUState *cs = env_cpu(env);
     if (!env->virt_enabled &&
@@ -566,7 +566,11 @@ void helper_tlb_flush(CPURISCVState *env)
                (env->priv == PRV_U || get_field(env->hstatus, HSTATUS_VTVM))) {
         riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
     } else {
-        tlb_flush(cs);
+        if (addr) {
+            tlb_flush_page(cs, addr);
+        } else {
+            tlb_flush(cs);
+        }
     }
 }

-- 
2.27.0

Re: [PATCH] target/riscv: Flush the TLB entry for the specified address

[Philippe Mathieu-Daudé]

Hi,

On 30/9/25 11:48, wang.yechao255@zte.com.cn wrote:
> From: yechao-w <wang.yechao255@zte.com.cn>
> 
> When the guest executes sfence/svinval with an address parameter,
> invalidating only the specific TLB entry for that address rather
> than the entire TLB enhances TCG performance.
> 
> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn>
> ---
>   target/riscv/helper.h                          | 2 +-
>   target/riscv/insn_trans/trans_privileged.c.inc | 4 +++-
>   target/riscv/insn_trans/trans_svinval.c.inc    | 4 +++-
>   target/riscv/op_helper.c                       | 8 ++++++--
>   4 files changed, 13 insertions(+), 5 deletions(-)


> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 110292e84d..0fe5fcb3ac 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -555,7 +555,7 @@ void helper_wrs_nto(CPURISCVState *env)
>       }
>   }
> 
> -void helper_tlb_flush(CPURISCVState *env)
> +void helper_tlb_flush(CPURISCVState *env, target_ulong addr)
>   {
>       CPUState *cs = env_cpu(env);
>       if (!env->virt_enabled &&
> @@ -566,7 +566,11 @@ void helper_tlb_flush(CPURISCVState *env)
>                  (env->priv == PRV_U || get_field(env->hstatus, HSTATUS_VTVM))) {
>           riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
>       } else {
> -        tlb_flush(cs);
> +        if (addr) {
> +            tlb_flush_page(cs, addr);

I suspect tlb_flush_page(cs, addr) is the right thing to do,
even for addr=0.

Can you point at the doc?

> +        } else {
> +            tlb_flush(cs);
> +        }
>       }
>   }
> 

Re: [PATCH] target/riscv: Flush the TLB entry for the specified address

[wang.yechao255]

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Hi Phil,
> > -void helper_tlb_flush(CPURISCVState *env)> > +void helper_tlb_flush(CPURISCVState *env, target_ulong addr)> >   {> >       CPUState *cs = env_cpu(env);> >       if (!env->virt_enabled &&> > @@ -566,7 +566,11 @@ void helper_tlb_flush(CPURISCVState *env)> >                  (env->priv == PRV_U || get_field(env->hstatus, HSTATUS_VTVM))) {> >           riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());> >       } else {> > -        tlb_flush(cs);> > +        if (addr) {> > +            tlb_flush_page(cs, addr);> I suspect tlb_flush_page(cs, addr) is the right thing to do,> even for addr=0.> > Can you point at the doc?
When addr=0, the current tlb_flush_page(cs, addr) does not flush all TLBs. 
Should tlb_flush_page(cs, addr) be extended to flush all TLBs when addr=0?

By the way, which document are you referring to here?

---
Best wishes
Yechao

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