Re: [PATCH v4 2/4] target/i386: add FZRM, FSRS, FSRC

[Xiaoyao Li <xiaoyao.li@intel.com>]

On 2/27/2023 6:13 PM, Paolo Bonzini wrote:
> These are three more markers for string operation optimizations.
> They can all be added to TCG, whose string operations are more or
> less as fast as they can be for short lengths.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>

> ---
>   target/i386/cpu.c | 7 ++++---
>   target/i386/cpu.h | 7 +++++++
>   2 files changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 34e2cead870e..26ec6e9da754 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -662,7 +662,8 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
>             /* CPUID_7_0_ECX_OSPKE is dynamic */ \
>             CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES)
>   #define TCG_7_0_EDX_FEATURES CPUID_7_0_EDX_FSRM
> -#define TCG_7_1_EAX_FEATURES 0
> +#define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \
> +          CPUID_7_1_EAX_FSRC)
>   #define TCG_APM_FEATURES 0
>   #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
>   #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
> @@ -872,8 +873,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
>           .feat_names = {
>               NULL, NULL, NULL, NULL,
>               "avx-vnni", "avx512-bf16", NULL, NULL,
> -            NULL, NULL, NULL, NULL,
> -            NULL, NULL, NULL, NULL,
> +            NULL, NULL, "fzrm", "fsrs",
> +            "fsrc", NULL, NULL, NULL,
>               NULL, NULL, NULL, NULL,
>               NULL, NULL, NULL, NULL,
>               NULL, NULL, NULL, NULL,
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index d4bc19577a21..e0703feb5ed0 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -900,6 +900,13 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
>   #define CPUID_7_1_EAX_AVX_VNNI          (1U << 4)
>   /* AVX512 BFloat16 Instruction */
>   #define CPUID_7_1_EAX_AVX512_BF16       (1U << 5)
> +/* Fast Zero REP MOVS */
> +#define CPUID_7_1_EAX_FZRM              (1U << 10)
> +/* Fast Short REP STOS */
> +#define CPUID_7_1_EAX_FSRS              (1U << 11)
> +/* Fast Short REP CMPS/SCAS */
> +#define CPUID_7_1_EAX_FSRC              (1U << 12)
> +
>   /* XFD Extend Feature Disabled */
>   #define CPUID_D_1_EAX_XFD               (1U << 4)
>