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d="scan'208";a="133782755" Received: from liuzhao-optiplex-7080.sh.intel.com (HELO localhost) ([10.239.160.39]) by orviesa007.jf.intel.com with ESMTP; 27 Apr 2025 01:33:51 -0700 Date: Sun, 27 Apr 2025 16:54:48 +0800 From: Zhao Liu To: Dapeng Mi Cc: Paolo Bonzini , Sean Christopherson , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zide Chen , Xiaoyao Li , Dongli Zhang , Mingwei Zhang , Das Sandipan , Shukla Manali , Dapeng Mi Subject: Re: [PATCH 3/3] target/i386: Support VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL Message-ID: References: <20250324123712.34096-1-dapeng1.mi@linux.intel.com> <20250324123712.34096-4-dapeng1.mi@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250324123712.34096-4-dapeng1.mi@linux.intel.com> Received-SPF: pass client-ip=192.198.163.11; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -50 X-Spam_score: -5.1 X-Spam_bar: ----- X-Spam_report: (-5.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.738, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org > @@ -4212,7 +4213,8 @@ static const X86CPUDefinition builtin_x86_defs[] = { > VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | > VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | > VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | > - VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, > + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | > + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, > .features[FEAT_VMX_MISC] = > MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | > MSR_VMX_MISC_VMWRITE_VMEXIT, > @@ -4368,7 +4370,8 @@ static const X86CPUDefinition builtin_x86_defs[] = { > VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | > VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | > VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | > - VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, > + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | > + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, > .features[FEAT_VMX_MISC] = > MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | > MSR_VMX_MISC_VMWRITE_VMEXIT, > @@ -4511,7 +4514,8 @@ static const X86CPUDefinition builtin_x86_defs[] = { > VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | > VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | > VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | > - VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, > + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | > + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL, > .features[FEAT_VMX_MISC] = > MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | > MSR_VMX_MISC_VMWRITE_VMEXIT, Instead of modifying SPR's CPU model directly, we should introduce a new version (SapphireRapids-v4), like Skylake-Server-v4 enables "vmx-eptp-switching".