* [PATCH for-10.1 v5 01/13] arm/cpu: Add sysreg definitions in cpu-sysregs.h
2025-04-09 14:42 [PATCH for-10.1 v5 00/13] arm: rework id register storage Cornelia Huck
@ 2025-04-09 14:42 ` Cornelia Huck
2025-04-09 14:42 ` [PATCH for-10.1 v5 02/13] arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays Cornelia Huck
` (12 subsequent siblings)
13 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-04-09 14:42 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
This new header contains macros that define aarch64 registers.
In a subsequent patch, this will be replaced by a more exhaustive
version that will be generated from linux arch/arm64/tools/sysreg
file. Those macros are sufficient to migrate the storage of those
ID regs from named fields in isar struct to an array cell.
[CH: reworked to use different structures]
[CH: moved accessors from the patches first using them to here,
dropped interaction with writable registers, which will happen
later]
[CH: use DEF magic suggested by rth]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-sysregs.h | 42 +++++++++++++++++++++++++++++++
target/arm/cpu-sysregs.h.inc | 35 ++++++++++++++++++++++++++
target/arm/cpu.h | 49 ++++++++++++++++++++++++++++++++++++
target/arm/cpu64.c | 22 ++++++++++++++++
4 files changed, 148 insertions(+)
create mode 100644 target/arm/cpu-sysregs.h
create mode 100644 target/arm/cpu-sysregs.h.inc
diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
new file mode 100644
index 000000000000..7877a3b06a8e
--- /dev/null
+++ b/target/arm/cpu-sysregs.h
@@ -0,0 +1,42 @@
+/*
+ * Definitions for Arm ID system registers
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef ARM_CPU_SYSREGS_H
+#define ARM_CPU_SYSREGS_H
+
+/*
+ * Following is similar to the coprocessor regs encodings, but with an argument
+ * ordering that matches the ARM ARM. We also reuse the various CP_REG_ defines
+ * that actually are the same as the equivalent KVM_REG_ values.
+ */
+#define ENCODE_ID_REG(op0, op1, crn, crm, op2) \
+ (((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
+ ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
+ ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
+ ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
+ ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
+
+#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) NAME##_IDX,
+
+typedef enum ARMIDRegisterIdx {
+#include "cpu-sysregs.h.inc"
+ NUM_ID_IDX,
+} ARMIDRegisterIdx;
+
+#undef DEF
+#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \
+ SYS_##NAME = ENCODE_ID_REG(OP0, OP1, CRN, CRM, OP2),
+
+typedef enum ARMSysRegs {
+#include "cpu-sysregs.h.inc"
+} ARMSysRegs;
+
+#undef DEF
+
+extern const uint32_t id_register_sysreg[NUM_ID_IDX];
+
+int get_sysreg_idx(ARMSysRegs sysreg);
+
+#endif /* ARM_CPU_SYSREGS_H */
diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
new file mode 100644
index 000000000000..6c9f9981cc5d
--- /dev/null
+++ b/target/arm/cpu-sysregs.h.inc
@@ -0,0 +1,35 @@
+DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
+DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
+DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)
+DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
+DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
+DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
+DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)
+DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2)
+DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0)
+DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)
+DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)
+DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3)
+DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0)
+DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1)
+DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2)
+DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4)
+DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5)
+DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6)
+DEF(ID_MMFR3_EL1, 3, 0, 0, 1, 7)
+DEF(ID_ISAR0_EL1, 3, 0, 0, 2, 0)
+DEF(ID_ISAR1_EL1, 3, 0, 0, 2, 1)
+DEF(ID_ISAR2_EL1, 3, 0, 0, 2, 2)
+DEF(ID_ISAR3_EL1, 3, 0, 0, 2, 3)
+DEF(ID_ISAR4_EL1, 3, 0, 0, 2, 4)
+DEF(ID_ISAR5_EL1, 3, 0, 0, 2, 5)
+DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6)
+DEF(ID_ISAR6_EL1, 3, 0, 0, 2, 7)
+DEF(MVFR0_EL1, 3, 0, 0, 3, 0)
+DEF(MVFR1_EL1, 3, 0, 0, 3, 1)
+DEF(MVFR2_EL1, 3, 0, 0, 3, 2)
+DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4)
+DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5)
+DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6)
+DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4)
+DEF(CTR_EL0, 3, 3, 0, 0, 1)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a8177c6c2e89..5048c85b188c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -30,6 +30,7 @@
#include "qapi/qapi-types-common.h"
#include "target/arm/multiprocessing.h"
#include "target/arm/gtimer.h"
+#include "target/arm/cpu-sysregs.h"
#ifdef TARGET_AARCH64
#define KVM_HAVE_MCE_INJECTION 1
@@ -855,6 +856,53 @@ typedef struct {
uint32_t map, init, supported;
} ARMVQMap;
+/* REG is ID_XXX */
+#define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \
+ ({ \
+ ARMISARegisters *i_ = (ISAR); \
+ uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \
+ regval = FIELD_DP64(regval, REG, FIELD, VALUE); \
+ i_->idregs[REG ## _EL1_IDX] = regval; \
+ })
+
+#define FIELD_DP32_IDREG(ISAR, REG, FIELD, VALUE) \
+ ({ \
+ ARMISARegisters *i_ = (ISAR); \
+ uint64_t regval = i_->idregs[REG ## _EL1_IDX]; \
+ regval = FIELD_DP32(regval, REG, FIELD, VALUE); \
+ i_->idregs[REG ## _EL1_IDX] = regval; \
+ })
+
+#define FIELD_EX64_IDREG(ISAR, REG, FIELD) \
+ ({ \
+ const ARMISARegisters *i_ = (ISAR); \
+ FIELD_EX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
+ })
+
+#define FIELD_EX32_IDREG(ISAR, REG, FIELD) \
+ ({ \
+ const ARMISARegisters *i_ = (ISAR); \
+ FIELD_EX32(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
+ })
+
+#define FIELD_SEX64_IDREG(ISAR, REG, FIELD) \
+ ({ \
+ const ARMISARegisters *i_ = (ISAR); \
+ FIELD_SEX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); \
+ })
+
+#define SET_IDREG(ISAR, REG, VALUE) \
+ ({ \
+ ARMISARegisters *i_ = (ISAR); \
+ i_->idregs[REG ## _EL1_IDX] = VALUE; \
+ })
+
+#define GET_IDREG(ISAR, REG) \
+ ({ \
+ const ARMISARegisters *i_ = (ISAR); \
+ i_->idregs[REG ## _EL1_IDX]; \
+ })
+
/**
* ARMCPU:
* @env: #CPUARMState
@@ -1063,6 +1111,7 @@ struct ArchCPU {
uint64_t id_aa64zfr0;
uint64_t id_aa64smfr0;
uint64_t reset_pmcr_el0;
+ uint64_t idregs[NUM_ID_IDX];
} isar;
uint64_t midr;
uint32_t revidr;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 8188ede5cc8a..62eff5375c19 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -36,6 +36,28 @@
#include "cpu-features.h"
#include "cpregs.h"
+/* convert between <register>_IDX and SYS_<register> */
+#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \
+ [NAME##_IDX] = SYS_##NAME,
+
+const uint32_t id_register_sysreg[NUM_ID_IDX] = {
+#include "cpu-sysregs.h.inc"
+};
+
+#undef DEF
+#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \
+ case SYS_##NAME: return NAME##_IDX;
+
+int get_sysreg_idx(ARMSysRegs sysreg)
+{
+ switch (sysreg) {
+#include "cpu-sysregs.h.inc"
+ }
+ g_assert_not_reached();
+}
+
+#undef DEF
+
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
{
/*
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH for-10.1 v5 02/13] arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays
2025-04-09 14:42 [PATCH for-10.1 v5 00/13] arm: rework id register storage Cornelia Huck
2025-04-09 14:42 ` [PATCH for-10.1 v5 01/13] arm/cpu: Add sysreg definitions in cpu-sysregs.h Cornelia Huck
@ 2025-04-09 14:42 ` Cornelia Huck
2025-04-28 14:52 ` Eric Auger
2025-05-13 15:41 ` Daniel P. Berrangé
2025-04-09 14:42 ` [PATCH for-10.1 v5 03/13] arm/cpu: Store aa64isar1/2 into the idregs array Cornelia Huck
` (11 subsequent siblings)
13 siblings, 2 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-04-09 14:42 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Also add kvm add accessors for storing host features into idregs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-features.h | 57 ++++++++++++++++++++-------------------
target/arm/cpu-sysregs.h | 4 +++
target/arm/cpu.c | 10 +++----
target/arm/cpu.h | 2 --
target/arm/cpu64.c | 8 +++---
target/arm/helper.c | 6 +++--
target/arm/hvf/hvf.c | 3 ++-
target/arm/kvm.c | 30 ++++++++++++++++++---
target/arm/tcg/cpu64.c | 44 ++++++++++++++++++------------
9 files changed, 101 insertions(+), 63 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 525e4cee12f6..779bcd1abb36 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -22,6 +22,7 @@
#include "hw/registerfields.h"
#include "qemu/host-utils.h"
+#include "cpu-sysregs.h"
/*
* Naming convention for isar_feature functions:
@@ -376,92 +377,92 @@ static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id)
*/
static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, AES) != 0;
}
static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, AES) > 1;
}
static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA1) != 0;
}
static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA2) != 0;
}
static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA2) > 1;
}
static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, CRC32) != 0;
}
static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) != 0;
}
static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RDM) != 0;
}
static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA3) != 0;
}
static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SM3) != 0;
}
static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SM4) != 0;
}
static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, DP) != 0;
}
static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, FHM) != 0;
}
static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TS) != 0;
}
static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TS) >= 2;
}
static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RNDR) != 0;
}
static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TLB) == 2;
}
static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TLB) != 0;
}
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
@@ -927,52 +928,52 @@ static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) != 0;
}
static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) != 0;
}
static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2;
+ return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) >= 2;
}
static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BITPERM) != 0;
}
static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BFLOAT16) != 0;
}
static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SHA3) != 0;
}
static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SM4) != 0;
}
static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ZFR0, I8MM) != 0;
}
static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ZFR0, F32MM) != 0;
}
static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ZFR0, F64MM) != 0;
}
static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id)
diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
index 7877a3b06a8e..e89a1105904c 100644
--- a/target/arm/cpu-sysregs.h
+++ b/target/arm/cpu-sysregs.h
@@ -39,4 +39,8 @@ extern const uint32_t id_register_sysreg[NUM_ID_IDX];
int get_sysreg_idx(ARMSysRegs sysreg);
+#ifdef CONFIG_KVM
+uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg);
+#endif
+
#endif /* ARM_CPU_SYSREGS_H */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 01786ac7879c..750a4e957cb2 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1968,6 +1968,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
ARMCPU *cpu = ARM_CPU(dev);
+ ARMISARegisters *isar = &cpu->isar;
ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
CPUARMState *env = &cpu->env;
Error *local_err = NULL;
@@ -2173,7 +2174,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
unset_feature(env, ARM_FEATURE_NEON);
- t = cpu->isar.id_aa64isar0;
+ t = GET_IDREG(isar, ID_AA64ISAR0);
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0);
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0);
t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0);
@@ -2181,7 +2182,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0);
t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0);
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
- cpu->isar.id_aa64isar0 = t;
+ SET_IDREG(isar, ID_AA64ISAR0, t);
t = cpu->isar.id_aa64isar1;
t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
@@ -2223,12 +2224,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
}
if (!cpu->has_neon && !cpu->has_vfp) {
- uint64_t t;
uint32_t u;
- t = cpu->isar.id_aa64isar0;
- t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
- cpu->isar.id_aa64isar0 = t;
+ FIELD_DP64_IDREG(isar, ID_AA64ISAR0, FHM, 0);
t = cpu->isar.id_aa64isar1;
t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5048c85b188c..57d00da0a927 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1097,7 +1097,6 @@ struct ArchCPU {
uint32_t dbgdidr;
uint32_t dbgdevid;
uint32_t dbgdevid1;
- uint64_t id_aa64isar0;
uint64_t id_aa64isar1;
uint64_t id_aa64isar2;
uint64_t id_aa64pfr0;
@@ -1108,7 +1107,6 @@ struct ArchCPU {
uint64_t id_aa64mmfr3;
uint64_t id_aa64dfr0;
uint64_t id_aa64dfr1;
- uint64_t id_aa64zfr0;
uint64_t id_aa64smfr0;
uint64_t reset_pmcr_el0;
uint64_t idregs[NUM_ID_IDX];
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 62eff5375c19..c781efeb7cef 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -136,7 +136,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
* SVE is disabled and so are all vector lengths. Good.
* Disable all SVE extensions as well.
*/
- cpu->isar.id_aa64zfr0 = 0;
+ SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0);
return;
}
@@ -639,6 +639,7 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
static void aarch64_a57_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,cortex-a57";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -676,7 +677,7 @@ static void aarch64_a57_initfn(Object *obj)
cpu->isar.id_isar6 = 0;
cpu->isar.id_aa64pfr0 = 0x00002222;
cpu->isar.id_aa64dfr0 = 0x10305106;
- cpu->isar.id_aa64isar0 = 0x00011120;
+ SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
cpu->isar.id_aa64mmfr0 = 0x00001124;
cpu->isar.dbgdidr = 0x3516d000;
cpu->isar.dbgdevid = 0x01110f13;
@@ -700,6 +701,7 @@ static void aarch64_a57_initfn(Object *obj)
static void aarch64_a53_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,cortex-a53";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -737,7 +739,7 @@ static void aarch64_a53_initfn(Object *obj)
cpu->isar.id_isar6 = 0;
cpu->isar.id_aa64pfr0 = 0x00002222;
cpu->isar.id_aa64dfr0 = 0x10305106;
- cpu->isar.id_aa64isar0 = 0x00011120;
+ SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
cpu->isar.dbgdidr = 0x3516d000;
cpu->isar.dbgdevid = 0x00110f13;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bb445e30cd15..8062e5190425 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7750,6 +7750,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{
/* Register all the coprocessor registers based on feature bits */
CPUARMState *env = &cpu->env;
+ ARMISARegisters *isar = &cpu->isar;
+
if (arm_feature(env, ARM_FEATURE_M)) {
/* M profile has no coprocessor registers */
return;
@@ -7939,7 +7941,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64zfr0 },
+ .resetvalue = GET_IDREG(isar, ID_AA64ZFR0)},
{ .name = "ID_AA64SMFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
@@ -7999,7 +8001,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64isar0 },
+ .resetvalue = GET_IDREG(isar, ID_AA64ISAR0)},
{ .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 2439af63a05a..0213702ef094 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -19,6 +19,7 @@
#include "system/hw_accel.h"
#include "hvf_arm.h"
#include "cpregs.h"
+#include "cpu-sysregs.h"
#include <mach/mach_time.h>
@@ -865,7 +866,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
{ HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 },
{ HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 },
{ HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },
- { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 },
+ { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] },
{ HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 },
/* Add ID_AA64ISAR2_EL1 here when HVF supports it */
{ HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index da30bdbb2349..d187df80f077 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -26,6 +26,7 @@
#include "system/kvm_int.h"
#include "kvm_arm.h"
#include "cpu.h"
+#include "cpu-sysregs.h"
#include "trace.h"
#include "internals.h"
#include "hw/pci/pci.h"
@@ -246,6 +247,28 @@ static bool kvm_arm_pauth_supported(void)
kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC));
}
+
+uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg)
+{
+ return ARM64_SYS_REG((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK) >> CP_REG_ARM64_SYSREG_OP0_SHIFT,
+ (sysreg & CP_REG_ARM64_SYSREG_OP1_MASK) >> CP_REG_ARM64_SYSREG_OP1_SHIFT,
+ (sysreg & CP_REG_ARM64_SYSREG_CRN_MASK) >> CP_REG_ARM64_SYSREG_CRN_SHIFT,
+ (sysreg & CP_REG_ARM64_SYSREG_CRM_MASK) >> CP_REG_ARM64_SYSREG_CRM_SHIFT,
+ (sysreg & CP_REG_ARM64_SYSREG_OP2_MASK) >> CP_REG_ARM64_SYSREG_OP2_SHIFT);
+}
+
+/* read a sysreg value and store it in the idregs */
+static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf, ARMIDRegisterIdx index)
+{
+ uint64_t *reg;
+ int ret;
+
+ reg = &ahcf->isar.idregs[index];
+ ret = read_sys_reg64(fd, reg,
+ idregs_sysreg_to_kvm_reg(id_register_sysreg[index]));
+ return ret;
+}
+
static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
{
/* Identify the feature bits corresponding to the host CPU, and
@@ -306,6 +329,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ahcf->target = init.target;
ahcf->dtb_compatible = "arm,arm-v8";
+ int fd = fdarray[2];
err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
ARM64_SYS_REG(3, 0, 0, 4, 0));
@@ -337,8 +361,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ARM64_SYS_REG(3, 0, 0, 5, 0));
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1,
ARM64_SYS_REG(3, 0, 0, 5, 1));
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0,
- ARM64_SYS_REG(3, 0, 0, 6, 0));
+ err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX);
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
ARM64_SYS_REG(3, 0, 0, 6, 1));
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2,
@@ -447,8 +470,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* enabled SVE support, which resulted in an error rather than RAZ.
* So only read the register if we set KVM_ARM_VCPU_SVE above.
*/
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
- ARM64_SYS_REG(3, 0, 0, 4, 4));
+ err |= get_host_cpu_reg(fd, ahcf, ID_AA64ZFR0_EL1_IDX);
}
}
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 29ab0ac79da9..f31bb9ceaac9 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -32,6 +32,7 @@
static void aarch64_a35_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,cortex-a35";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -66,7 +67,7 @@ static void aarch64_a35_initfn(Object *obj)
cpu->isar.id_aa64pfr1 = 0;
cpu->isar.id_aa64dfr0 = 0x10305106;
cpu->isar.id_aa64dfr1 = 0;
- cpu->isar.id_aa64isar0 = 0x00011120;
+ SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
cpu->isar.id_aa64isar1 = 0;
cpu->isar.id_aa64mmfr0 = 0x00101122;
cpu->isar.id_aa64mmfr1 = 0;
@@ -204,6 +205,7 @@ static const Property arm_cpu_lpa2_property =
static void aarch64_a55_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,cortex-a55";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -221,7 +223,7 @@ static void aarch64_a55_initfn(Object *obj)
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
cpu->dcz_blocksize = 4; /* 64 bytes */
cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+ SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
@@ -276,6 +278,7 @@ static void aarch64_a55_initfn(Object *obj)
static void aarch64_a72_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,cortex-a72";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -311,7 +314,7 @@ static void aarch64_a72_initfn(Object *obj)
cpu->isar.id_isar5 = 0x00011121;
cpu->isar.id_aa64pfr0 = 0x00002222;
cpu->isar.id_aa64dfr0 = 0x10305106;
- cpu->isar.id_aa64isar0 = 0x00011120;
+ SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
cpu->isar.id_aa64mmfr0 = 0x00001124;
cpu->isar.dbgdidr = 0x3516d000;
cpu->isar.dbgdevid = 0x01110f13;
@@ -335,6 +338,7 @@ static void aarch64_a72_initfn(Object *obj)
static void aarch64_a76_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,cortex-a76";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -352,7 +356,7 @@ static void aarch64_a76_initfn(Object *obj)
cpu->ctr = 0x8444C004;
cpu->dcz_blocksize = 4;
cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+ SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
@@ -408,6 +412,7 @@ static void aarch64_a76_initfn(Object *obj)
static void aarch64_a64fx_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,a64fx";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -431,9 +436,9 @@ static void aarch64_a64fx_initfn(Object *obj)
cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
- cpu->isar.id_aa64isar0 = 0x0000000010211120;
+ SET_IDREG(isar, ID_AA64ISAR0, 0x0000000010211120);
cpu->isar.id_aa64isar1 = 0x0000000000010001;
- cpu->isar.id_aa64zfr0 = 0x0000000000000000;
+ SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000);
cpu->clidr = 0x0000000080000023;
/* 64KB L1 dcache */
cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 7);
@@ -581,6 +586,7 @@ static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu)
static void aarch64_neoverse_n1_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,neoverse-n1";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -598,7 +604,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
cpu->ctr = 0x8444c004;
cpu->dcz_blocksize = 4;
cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+ SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
@@ -656,6 +662,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
static void aarch64_neoverse_v1_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,neoverse-v1";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -676,7 +683,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->id_aa64afr1 = 0x00000000;
cpu->isar.id_aa64dfr0 = 0x000001f210305519ull;
cpu->isar.id_aa64dfr1 = 0x00000000;
- cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */
+ SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */
cpu->isar.id_aa64isar1 = 0x0011100001211032ull;
cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
@@ -735,7 +742,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043;
/* From 3.7.5 ID_AA64ZFR0_EL1 */
- cpu->isar.id_aa64zfr0 = 0x0000100000100000;
+ SET_IDREG(isar, ID_AA64ZFR0, 0x0000100000100000);
cpu->sve_vq.supported = (1 << 0) /* 128bit */
| (1 << 1); /* 256bit */
@@ -882,6 +889,7 @@ static const ARMCPRegInfo cortex_a710_cp_reginfo[] = {
static void aarch64_a710_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,cortex-a710";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -919,12 +927,12 @@ static void aarch64_a710_initfn(Object *obj)
cpu->isar.id_pfr2 = 0x00000011;
cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
- cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */
+ SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
cpu->isar.id_aa64dfr0 = 0x000011f010305619ull;
cpu->isar.id_aa64dfr1 = 0;
cpu->id_aa64afr0 = 0;
cpu->id_aa64afr1 = 0;
- cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */
+ SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */
cpu->isar.id_aa64isar1 = 0x0010111101211052ull;
cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
@@ -983,6 +991,7 @@ static const ARMCPRegInfo neoverse_n2_cp_reginfo[] = {
static void aarch64_neoverse_n2_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,neoverse-n2";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -1020,12 +1029,12 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->isar.id_pfr2 = 0x00000011;
cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
- cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */
+ SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
cpu->isar.id_aa64dfr0 = 0x000011f210305619ull;
cpu->isar.id_aa64dfr1 = 0;
cpu->id_aa64afr0 = 0;
cpu->id_aa64afr1 = 0;
- cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */
+ SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto and FEAT_RNG */
cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
@@ -1083,6 +1092,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
void aarch64_max_tcg_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
uint64_t t;
uint32_t u;
@@ -1133,7 +1143,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, CTR_EL0, DIC, 1);
cpu->ctr = t;
- t = cpu->isar.id_aa64isar0;
+ t = GET_IDREG(isar, ID_AA64ISAR0);
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
@@ -1148,7 +1158,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
- cpu->isar.id_aa64isar0 = t;
+ SET_IDREG(isar, ID_AA64ISAR0, t);
t = cpu->isar.id_aa64isar1;
t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
@@ -1244,7 +1254,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */
cpu->isar.id_aa64mmfr3 = t;
- t = cpu->isar.id_aa64zfr0;
+ t = GET_IDREG(isar, ID_AA64ZFR0);
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
@@ -1254,7 +1264,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
- cpu->isar.id_aa64zfr0 = t;
+ SET_IDREG(isar, ID_AA64ZFR0, t);
t = cpu->isar.id_aa64dfr0;
t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH for-10.1 v5 02/13] arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays
2025-04-09 14:42 ` [PATCH for-10.1 v5 02/13] arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays Cornelia Huck
@ 2025-04-28 14:52 ` Eric Auger
2025-04-29 9:31 ` Cornelia Huck
2025-05-13 15:41 ` Daniel P. Berrangé
1 sibling, 1 reply; 29+ messages in thread
From: Eric Auger @ 2025-04-28 14:52 UTC (permalink / raw)
To: Cornelia Huck, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini
Hi Connie,
On 4/9/25 4:42 PM, Cornelia Huck wrote:
> From: Eric Auger <eric.auger@redhat.com>
>
> Also add kvm add accessors for storing host features into idregs.
nit: add kvm add?
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Sebastian Ott <sebott@redhat.com>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
> ---
> target/arm/cpu-features.h | 57 ++++++++++++++++++++-------------------
> target/arm/cpu-sysregs.h | 4 +++
> target/arm/cpu.c | 10 +++----
> target/arm/cpu.h | 2 --
> target/arm/cpu64.c | 8 +++---
> target/arm/helper.c | 6 +++--
> target/arm/hvf/hvf.c | 3 ++-
> target/arm/kvm.c | 30 ++++++++++++++++++---
> target/arm/tcg/cpu64.c | 44 ++++++++++++++++++------------
> 9 files changed, 101 insertions(+), 63 deletions(-)
>
> diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
> index 525e4cee12f6..779bcd1abb36 100644
> --- a/target/arm/cpu-features.h
> +++ b/target/arm/cpu-features.h
> @@ -22,6 +22,7 @@
>
> #include "hw/registerfields.h"
> #include "qemu/host-utils.h"
> +#include "cpu-sysregs.h"
>
> /*
> * Naming convention for isar_feature functions:
> @@ -376,92 +377,92 @@ static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id)
> */
> static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, AES) != 0;
> }
>
> static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, AES) > 1;
> }
>
> static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA1) != 0;
> }
>
> static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA2) != 0;
> }
>
> static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA2) > 1;
> }
>
> static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, CRC32) != 0;
> }
>
> static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) != 0;
> }
>
> static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RDM) != 0;
> }
>
> static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA3) != 0;
> }
>
> static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SM3) != 0;
> }
>
> static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SM4) != 0;
> }
>
> static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, DP) != 0;
> }
>
> static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, FHM) != 0;
> }
>
> static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TS) != 0;
> }
>
> static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TS) >= 2;
> }
>
> static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RNDR) != 0;
> }
>
> static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TLB) == 2;
> }
>
> static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TLB) != 0;
> }
>
> static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
> @@ -927,52 +928,52 @@ static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
>
> static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SVEVER) != 0;
> }
>
> static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) != 0;
> }
>
> static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2;
> + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, AES) >= 2;
> }
>
> static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BITPERM) != 0;
> }
>
> static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BFLOAT16) != 0;
> }
>
> static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SHA3) != 0;
> }
>
> static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SM4) != 0;
> }
>
> static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, I8MM) != 0;
> }
>
> static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, F32MM) != 0;
> }
>
> static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ZFR0, F64MM) != 0;
> }
>
> static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id)
> diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
> index 7877a3b06a8e..e89a1105904c 100644
> --- a/target/arm/cpu-sysregs.h
> +++ b/target/arm/cpu-sysregs.h
> @@ -39,4 +39,8 @@ extern const uint32_t id_register_sysreg[NUM_ID_IDX];
>
> int get_sysreg_idx(ARMSysRegs sysreg);
>
> +#ifdef CONFIG_KVM
> +uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg);
> +#endif
> +
> #endif /* ARM_CPU_SYSREGS_H */
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 01786ac7879c..750a4e957cb2 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1968,6 +1968,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> {
> CPUState *cs = CPU(dev);
> ARMCPU *cpu = ARM_CPU(dev);
> + ARMISARegisters *isar = &cpu->isar;
> ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
> CPUARMState *env = &cpu->env;
> Error *local_err = NULL;
> @@ -2173,7 +2174,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
>
> unset_feature(env, ARM_FEATURE_NEON);
>
> - t = cpu->isar.id_aa64isar0;
> + t = GET_IDREG(isar, ID_AA64ISAR0);
> t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0);
> t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0);
> t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0);
> @@ -2181,7 +2182,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0);
> t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0);
> t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
> - cpu->isar.id_aa64isar0 = t;
> + SET_IDREG(isar, ID_AA64ISAR0, t);
>
> t = cpu->isar.id_aa64isar1;
> t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
> @@ -2223,12 +2224,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> }
>
> if (!cpu->has_neon && !cpu->has_vfp) {
> - uint64_t t;
> uint32_t u;
>
> - t = cpu->isar.id_aa64isar0;
> - t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
> - cpu->isar.id_aa64isar0 = t;
> + FIELD_DP64_IDREG(isar, ID_AA64ISAR0, FHM, 0);
>
> t = cpu->isar.id_aa64isar1;
> t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 5048c85b188c..57d00da0a927 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1097,7 +1097,6 @@ struct ArchCPU {
> uint32_t dbgdidr;
> uint32_t dbgdevid;
> uint32_t dbgdevid1;
> - uint64_t id_aa64isar0;
> uint64_t id_aa64isar1;
> uint64_t id_aa64isar2;
> uint64_t id_aa64pfr0;
> @@ -1108,7 +1107,6 @@ struct ArchCPU {
> uint64_t id_aa64mmfr3;
> uint64_t id_aa64dfr0;
> uint64_t id_aa64dfr1;
> - uint64_t id_aa64zfr0;
> uint64_t id_aa64smfr0;
> uint64_t reset_pmcr_el0;
> uint64_t idregs[NUM_ID_IDX];
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 62eff5375c19..c781efeb7cef 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -136,7 +136,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
> * SVE is disabled and so are all vector lengths. Good.
> * Disable all SVE extensions as well.
> */
> - cpu->isar.id_aa64zfr0 = 0;
> + SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0);
> return;
> }
>
> @@ -639,6 +639,7 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
> static void aarch64_a57_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,cortex-a57";
> set_feature(&cpu->env, ARM_FEATURE_V8);
> @@ -676,7 +677,7 @@ static void aarch64_a57_initfn(Object *obj)
> cpu->isar.id_isar6 = 0;
> cpu->isar.id_aa64pfr0 = 0x00002222;
> cpu->isar.id_aa64dfr0 = 0x10305106;
> - cpu->isar.id_aa64isar0 = 0x00011120;
> + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> cpu->isar.id_aa64mmfr0 = 0x00001124;
> cpu->isar.dbgdidr = 0x3516d000;
> cpu->isar.dbgdevid = 0x01110f13;
> @@ -700,6 +701,7 @@ static void aarch64_a57_initfn(Object *obj)
> static void aarch64_a53_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,cortex-a53";
> set_feature(&cpu->env, ARM_FEATURE_V8);
> @@ -737,7 +739,7 @@ static void aarch64_a53_initfn(Object *obj)
> cpu->isar.id_isar6 = 0;
> cpu->isar.id_aa64pfr0 = 0x00002222;
> cpu->isar.id_aa64dfr0 = 0x10305106;
> - cpu->isar.id_aa64isar0 = 0x00011120;
> + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
> cpu->isar.dbgdidr = 0x3516d000;
> cpu->isar.dbgdevid = 0x00110f13;
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index bb445e30cd15..8062e5190425 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -7750,6 +7750,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> {
> /* Register all the coprocessor registers based on feature bits */
> CPUARMState *env = &cpu->env;
> + ARMISARegisters *isar = &cpu->isar;
> +
> if (arm_feature(env, ARM_FEATURE_M)) {
> /* M profile has no coprocessor registers */
> return;
> @@ -7939,7 +7941,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa64_tid3,
> - .resetvalue = cpu->isar.id_aa64zfr0 },
> + .resetvalue = GET_IDREG(isar, ID_AA64ZFR0)},
> { .name = "ID_AA64SMFR0_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
> .access = PL1_R, .type = ARM_CP_CONST,
> @@ -7999,7 +8001,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa64_tid3,
> - .resetvalue = cpu->isar.id_aa64isar0 },
> + .resetvalue = GET_IDREG(isar, ID_AA64ISAR0)},
> { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
> .access = PL1_R, .type = ARM_CP_CONST,
> diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
> index 2439af63a05a..0213702ef094 100644
> --- a/target/arm/hvf/hvf.c
> +++ b/target/arm/hvf/hvf.c
> @@ -19,6 +19,7 @@
> #include "system/hw_accel.h"
> #include "hvf_arm.h"
> #include "cpregs.h"
> +#include "cpu-sysregs.h"
>
> #include <mach/mach_time.h>
>
> @@ -865,7 +866,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 },
> { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 },
> { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },
> - { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 },
> + { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] },
> { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 },
> /* Add ID_AA64ISAR2_EL1 here when HVF supports it */
> { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
> diff --git a/target/arm/kvm.c b/target/arm/kvm.c
> index da30bdbb2349..d187df80f077 100644
> --- a/target/arm/kvm.c
> +++ b/target/arm/kvm.c
> @@ -26,6 +26,7 @@
> #include "system/kvm_int.h"
> #include "kvm_arm.h"
> #include "cpu.h"
> +#include "cpu-sysregs.h"
> #include "trace.h"
> #include "internals.h"
> #include "hw/pci/pci.h"
> @@ -246,6 +247,28 @@ static bool kvm_arm_pauth_supported(void)
> kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC));
> }
>
> +
> +uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg)
> +{
> + return ARM64_SYS_REG((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK) >> CP_REG_ARM64_SYSREG_OP0_SHIFT,
> + (sysreg & CP_REG_ARM64_SYSREG_OP1_MASK) >> CP_REG_ARM64_SYSREG_OP1_SHIFT,
> + (sysreg & CP_REG_ARM64_SYSREG_CRN_MASK) >> CP_REG_ARM64_SYSREG_CRN_SHIFT,
> + (sysreg & CP_REG_ARM64_SYSREG_CRM_MASK) >> CP_REG_ARM64_SYSREG_CRM_SHIFT,
> + (sysreg & CP_REG_ARM64_SYSREG_OP2_MASK) >> CP_REG_ARM64_SYSREG_OP2_SHIFT);
> +}
> +
> +/* read a sysreg value and store it in the idregs */
> +static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf, ARMIDRegisterIdx index)
> +{
> + uint64_t *reg;
> + int ret;
> +
> + reg = &ahcf->isar.idregs[index];
> + ret = read_sys_reg64(fd, reg,
> + idregs_sysreg_to_kvm_reg(id_register_sysreg[index]));
> + return ret;
> +}
> +
> static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> {
> /* Identify the feature bits corresponding to the host CPU, and
> @@ -306,6 +329,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
>
> ahcf->target = init.target;
> ahcf->dtb_compatible = "arm,arm-v8";
> + int fd = fdarray[2];
>
> err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
> ARM64_SYS_REG(3, 0, 0, 4, 0));
> @@ -337,8 +361,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> ARM64_SYS_REG(3, 0, 0, 5, 0));
> err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1,
> ARM64_SYS_REG(3, 0, 0, 5, 1));
> - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0,
while at it you could add use fd in this other calls instead of
fdarray[2]. But this can be done later.
> - ARM64_SYS_REG(3, 0, 0, 6, 0));
> + err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX);
> err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
> ARM64_SYS_REG(3, 0, 0, 6, 1));
> err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2,
> @@ -447,8 +470,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> * enabled SVE support, which resulted in an error rather than RAZ.
> * So only read the register if we set KVM_ARM_VCPU_SVE above.
> */
> - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
> - ARM64_SYS_REG(3, 0, 0, 4, 4));
> + err |= get_host_cpu_reg(fd, ahcf, ID_AA64ZFR0_EL1_IDX);
> }
> }
>
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index 29ab0ac79da9..f31bb9ceaac9 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -32,6 +32,7 @@
> static void aarch64_a35_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,cortex-a35";
> set_feature(&cpu->env, ARM_FEATURE_V8);
> @@ -66,7 +67,7 @@ static void aarch64_a35_initfn(Object *obj)
> cpu->isar.id_aa64pfr1 = 0;
> cpu->isar.id_aa64dfr0 = 0x10305106;
> cpu->isar.id_aa64dfr1 = 0;
> - cpu->isar.id_aa64isar0 = 0x00011120;
> + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> cpu->isar.id_aa64isar1 = 0;
> cpu->isar.id_aa64mmfr0 = 0x00101122;
> cpu->isar.id_aa64mmfr1 = 0;
> @@ -204,6 +205,7 @@ static const Property arm_cpu_lpa2_property =
> static void aarch64_a55_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,cortex-a55";
> set_feature(&cpu->env, ARM_FEATURE_V8);
> @@ -221,7 +223,7 @@ static void aarch64_a55_initfn(Object *obj)
> cpu->ctr = 0x84448004; /* L1Ip = VIPT */
> cpu->dcz_blocksize = 4; /* 64 bytes */
> cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
> - cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
> + SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
> cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
> cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> @@ -276,6 +278,7 @@ static void aarch64_a55_initfn(Object *obj)
> static void aarch64_a72_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,cortex-a72";
> set_feature(&cpu->env, ARM_FEATURE_V8);
> @@ -311,7 +314,7 @@ static void aarch64_a72_initfn(Object *obj)
> cpu->isar.id_isar5 = 0x00011121;
> cpu->isar.id_aa64pfr0 = 0x00002222;
> cpu->isar.id_aa64dfr0 = 0x10305106;
> - cpu->isar.id_aa64isar0 = 0x00011120;
> + SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> cpu->isar.id_aa64mmfr0 = 0x00001124;
> cpu->isar.dbgdidr = 0x3516d000;
> cpu->isar.dbgdevid = 0x01110f13;
> @@ -335,6 +338,7 @@ static void aarch64_a72_initfn(Object *obj)
> static void aarch64_a76_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,cortex-a76";
> set_feature(&cpu->env, ARM_FEATURE_V8);
> @@ -352,7 +356,7 @@ static void aarch64_a76_initfn(Object *obj)
> cpu->ctr = 0x8444C004;
> cpu->dcz_blocksize = 4;
> cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
> - cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
> + SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
> cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
> cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> @@ -408,6 +412,7 @@ static void aarch64_a76_initfn(Object *obj)
> static void aarch64_a64fx_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,a64fx";
> set_feature(&cpu->env, ARM_FEATURE_V8);
> @@ -431,9 +436,9 @@ static void aarch64_a64fx_initfn(Object *obj)
> cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
> cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
> cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
> - cpu->isar.id_aa64isar0 = 0x0000000010211120;
> + SET_IDREG(isar, ID_AA64ISAR0, 0x0000000010211120);
> cpu->isar.id_aa64isar1 = 0x0000000000010001;
> - cpu->isar.id_aa64zfr0 = 0x0000000000000000;
> + SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000);
> cpu->clidr = 0x0000000080000023;
> /* 64KB L1 dcache */
> cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 7);
> @@ -581,6 +586,7 @@ static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu)
> static void aarch64_neoverse_n1_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,neoverse-n1";
> set_feature(&cpu->env, ARM_FEATURE_V8);
> @@ -598,7 +604,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
> cpu->ctr = 0x8444c004;
> cpu->dcz_blocksize = 4;
> cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
> - cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
> + SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
> cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
> cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> @@ -656,6 +662,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
> static void aarch64_neoverse_v1_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,neoverse-v1";
> set_feature(&cpu->env, ARM_FEATURE_V8);
> @@ -676,7 +683,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
> cpu->id_aa64afr1 = 0x00000000;
> cpu->isar.id_aa64dfr0 = 0x000001f210305519ull;
> cpu->isar.id_aa64dfr1 = 0x00000000;
> - cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */
> + SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */
> cpu->isar.id_aa64isar1 = 0x0011100001211032ull;
> cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> @@ -735,7 +742,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
> cpu->isar.mvfr2 = 0x00000043;
>
> /* From 3.7.5 ID_AA64ZFR0_EL1 */
> - cpu->isar.id_aa64zfr0 = 0x0000100000100000;
> + SET_IDREG(isar, ID_AA64ZFR0, 0x0000100000100000);
> cpu->sve_vq.supported = (1 << 0) /* 128bit */
> | (1 << 1); /* 256bit */
>
> @@ -882,6 +889,7 @@ static const ARMCPRegInfo cortex_a710_cp_reginfo[] = {
> static void aarch64_a710_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,cortex-a710";
> set_feature(&cpu->env, ARM_FEATURE_V8);
> @@ -919,12 +927,12 @@ static void aarch64_a710_initfn(Object *obj)
> cpu->isar.id_pfr2 = 0x00000011;
> cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
> cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
> - cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */
> + SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
> cpu->isar.id_aa64dfr0 = 0x000011f010305619ull;
> cpu->isar.id_aa64dfr1 = 0;
> cpu->id_aa64afr0 = 0;
> cpu->id_aa64afr1 = 0;
> - cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */
> + SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */
> cpu->isar.id_aa64isar1 = 0x0010111101211052ull;
> cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> @@ -983,6 +991,7 @@ static const ARMCPRegInfo neoverse_n2_cp_reginfo[] = {
> static void aarch64_neoverse_n2_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,neoverse-n2";
> set_feature(&cpu->env, ARM_FEATURE_V8);
> @@ -1020,12 +1029,12 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
> cpu->isar.id_pfr2 = 0x00000011;
> cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
> cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
> - cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */
> + SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
> cpu->isar.id_aa64dfr0 = 0x000011f210305619ull;
> cpu->isar.id_aa64dfr1 = 0;
> cpu->id_aa64afr0 = 0;
> cpu->id_aa64afr1 = 0;
> - cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */
> + SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto and FEAT_RNG */
> cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
> cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> @@ -1083,6 +1092,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
> void aarch64_max_tcg_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
> uint64_t t;
> uint32_t u;
>
> @@ -1133,7 +1143,7 @@ void aarch64_max_tcg_initfn(Object *obj)
> t = FIELD_DP64(t, CTR_EL0, DIC, 1);
> cpu->ctr = t;
>
> - t = cpu->isar.id_aa64isar0;
> + t = GET_IDREG(isar, ID_AA64ISAR0);
> t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
> t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
> t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
> @@ -1148,7 +1158,7 @@ void aarch64_max_tcg_initfn(Object *obj)
> t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
> t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
> t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
> - cpu->isar.id_aa64isar0 = t;
> + SET_IDREG(isar, ID_AA64ISAR0, t);
>
> t = cpu->isar.id_aa64isar1;
> t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
> @@ -1244,7 +1254,7 @@ void aarch64_max_tcg_initfn(Object *obj)
> t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */
> cpu->isar.id_aa64mmfr3 = t;
>
> - t = cpu->isar.id_aa64zfr0;
> + t = GET_IDREG(isar, ID_AA64ZFR0);
> t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
> t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
> t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
> @@ -1254,7 +1264,7 @@ void aarch64_max_tcg_initfn(Object *obj)
> t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
> t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
> t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
> - cpu->isar.id_aa64zfr0 = t;
> + SET_IDREG(isar, ID_AA64ZFR0, t);
>
> t = cpu->isar.id_aa64dfr0;
> t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */
Thanks
Eric
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH for-10.1 v5 02/13] arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays
2025-04-28 14:52 ` Eric Auger
@ 2025-04-29 9:31 ` Cornelia Huck
0 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-04-29 9:31 UTC (permalink / raw)
To: eric.auger, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini
On Mon, Apr 28 2025, Eric Auger <eric.auger@redhat.com> wrote:
> Hi Connie,
>
> On 4/9/25 4:42 PM, Cornelia Huck wrote:
>> From: Eric Auger <eric.auger@redhat.com>
>>
>> Also add kvm add accessors for storing host features into idregs.
> nit: add kvm add?
Too much adding, will substract one add :)
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Reviewed-by: Sebastian Ott <sebott@redhat.com>
>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
>> ---
>> target/arm/cpu-features.h | 57 ++++++++++++++++++++-------------------
>> target/arm/cpu-sysregs.h | 4 +++
>> target/arm/cpu.c | 10 +++----
>> target/arm/cpu.h | 2 --
>> target/arm/cpu64.c | 8 +++---
>> target/arm/helper.c | 6 +++--
>> target/arm/hvf/hvf.c | 3 ++-
>> target/arm/kvm.c | 30 ++++++++++++++++++---
>> target/arm/tcg/cpu64.c | 44 ++++++++++++++++++------------
>> 9 files changed, 101 insertions(+), 63 deletions(-)
>> @@ -337,8 +361,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
>> ARM64_SYS_REG(3, 0, 0, 5, 0));
>> err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1,
>> ARM64_SYS_REG(3, 0, 0, 5, 1));
>> - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0,
> while at it you could add use fd in this other calls instead of
> fdarray[2]. But this can be done later.
Given that this series needs a respin anyway, might as well do that.
>> - ARM64_SYS_REG(3, 0, 0, 6, 0));
>> + err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX);
>> err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
>> ARM64_SYS_REG(3, 0, 0, 6, 1));
>> err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2,
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH for-10.1 v5 02/13] arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays
2025-04-09 14:42 ` [PATCH for-10.1 v5 02/13] arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays Cornelia Huck
2025-04-28 14:52 ` Eric Auger
@ 2025-05-13 15:41 ` Daniel P. Berrangé
2025-05-13 15:56 ` Cornelia Huck
1 sibling, 1 reply; 29+ messages in thread
From: Daniel P. Berrangé @ 2025-05-13 15:41 UTC (permalink / raw)
To: Cornelia Huck
Cc: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, abologna, jdenemar,
agraf, shahuang, mark.rutland, philmd, pbonzini
On Wed, Apr 09, 2025 at 04:42:53PM +0200, Cornelia Huck wrote:
> From: Eric Auger <eric.auger@redhat.com>
>
> Also add kvm add accessors for storing host features into idregs.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Sebastian Ott <sebott@redhat.com>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
> ---
> target/arm/cpu-features.h | 57 ++++++++++++++++++++-------------------
> target/arm/cpu-sysregs.h | 4 +++
> target/arm/cpu.c | 10 +++----
> target/arm/cpu.h | 2 --
> target/arm/cpu64.c | 8 +++---
> target/arm/helper.c | 6 +++--
> target/arm/hvf/hvf.c | 3 ++-
> target/arm/kvm.c | 30 ++++++++++++++++++---
> target/arm/tcg/cpu64.c | 44 ++++++++++++++++++------------
> 9 files changed, 101 insertions(+), 63 deletions(-)
> diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
> index 7877a3b06a8e..e89a1105904c 100644
> --- a/target/arm/cpu-sysregs.h
> +++ b/target/arm/cpu-sysregs.h
> @@ -39,4 +39,8 @@ extern const uint32_t id_register_sysreg[NUM_ID_IDX];
>
> int get_sysreg_idx(ARMSysRegs sysreg);
>
> +#ifdef CONFIG_KVM
> +uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg);
> +#endif
This breaks the build when KVM is disabled, and/or not available
on the build target architecture
In file included from ../target/arm/cpu.h:35,
from /var/home/berrange/src/virt/qemu/include/hw/arm/digic.h:21,
from ../hw/arm/digic_boards.c:31:
/var/home/berrange/src/virt/qemu/target/arm/cpu-sysregs.h:42:8: error: attempt to use poisoned ‘CONFIG_KVM’
42 | #ifdef CONFIG_KVM
| ^
In file included from /var/home/berrange/src/virt/qemu/include/exec/poison.h:7,
from /var/home/berrange/src/virt/qemu/include/qemu/osdep.h:38,
from ../hw/arm/digic_boards.c:26:
./config-poison.h:185:20: note: poisoned here
185 | #pragma GCC poison CONFIG_KVM
| ^~~~~~~~~~
ninja: build stopped: subcommand failed.
With regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o- https://fstop138.berrange.com :|
|: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH for-10.1 v5 02/13] arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays
2025-05-13 15:41 ` Daniel P. Berrangé
@ 2025-05-13 15:56 ` Cornelia Huck
2025-05-13 16:17 ` Daniel P. Berrangé
0 siblings, 1 reply; 29+ messages in thread
From: Cornelia Huck @ 2025-05-13 15:56 UTC (permalink / raw)
To: Daniel P. Berrangé
Cc: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, abologna, jdenemar,
agraf, shahuang, mark.rutland, philmd, pbonzini
On Tue, May 13 2025, Daniel P. Berrangé <berrange@redhat.com> wrote:
> On Wed, Apr 09, 2025 at 04:42:53PM +0200, Cornelia Huck wrote:
>> From: Eric Auger <eric.auger@redhat.com>
>>
>> Also add kvm add accessors for storing host features into idregs.
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Reviewed-by: Sebastian Ott <sebott@redhat.com>
>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
>> ---
>> target/arm/cpu-features.h | 57 ++++++++++++++++++++-------------------
>> target/arm/cpu-sysregs.h | 4 +++
>> target/arm/cpu.c | 10 +++----
>> target/arm/cpu.h | 2 --
>> target/arm/cpu64.c | 8 +++---
>> target/arm/helper.c | 6 +++--
>> target/arm/hvf/hvf.c | 3 ++-
>> target/arm/kvm.c | 30 ++++++++++++++++++---
>> target/arm/tcg/cpu64.c | 44 ++++++++++++++++++------------
>> 9 files changed, 101 insertions(+), 63 deletions(-)
>
>> diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
>> index 7877a3b06a8e..e89a1105904c 100644
>> --- a/target/arm/cpu-sysregs.h
>> +++ b/target/arm/cpu-sysregs.h
>> @@ -39,4 +39,8 @@ extern const uint32_t id_register_sysreg[NUM_ID_IDX];
>>
>> int get_sysreg_idx(ARMSysRegs sysreg);
>>
>> +#ifdef CONFIG_KVM
>> +uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg);
>> +#endif
>
> This breaks the build when KVM is disabled, and/or not available
> on the build target architecture
>
> In file included from ../target/arm/cpu.h:35,
> from /var/home/berrange/src/virt/qemu/include/hw/arm/digic.h:21,
> from ../hw/arm/digic_boards.c:31:
> /var/home/berrange/src/virt/qemu/target/arm/cpu-sysregs.h:42:8: error: attempt to use poisoned ‘CONFIG_KVM’
> 42 | #ifdef CONFIG_KVM
> | ^
> In file included from /var/home/berrange/src/virt/qemu/include/exec/poison.h:7,
> from /var/home/berrange/src/virt/qemu/include/qemu/osdep.h:38,
> from ../hw/arm/digic_boards.c:26:
> ./config-poison.h:185:20: note: poisoned here
> 185 | #pragma GCC poison CONFIG_KVM
> | ^~~~~~~~~~
> ninja: build stopped: subcommand failed.
I have already fixed that one in v6.
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH for-10.1 v5 02/13] arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays
2025-05-13 15:56 ` Cornelia Huck
@ 2025-05-13 16:17 ` Daniel P. Berrangé
0 siblings, 0 replies; 29+ messages in thread
From: Daniel P. Berrangé @ 2025-05-13 16:17 UTC (permalink / raw)
To: Cornelia Huck
Cc: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, abologna, jdenemar,
agraf, shahuang, mark.rutland, philmd, pbonzini
On Tue, May 13, 2025 at 05:56:46PM +0200, Cornelia Huck wrote:
> On Tue, May 13 2025, Daniel P. Berrangé <berrange@redhat.com> wrote:
>
> > On Wed, Apr 09, 2025 at 04:42:53PM +0200, Cornelia Huck wrote:
> >> From: Eric Auger <eric.auger@redhat.com>
> >>
> >> Also add kvm add accessors for storing host features into idregs.
> >>
> >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> >> Reviewed-by: Sebastian Ott <sebott@redhat.com>
> >> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> >> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
> >> ---
> >> target/arm/cpu-features.h | 57 ++++++++++++++++++++-------------------
> >> target/arm/cpu-sysregs.h | 4 +++
> >> target/arm/cpu.c | 10 +++----
> >> target/arm/cpu.h | 2 --
> >> target/arm/cpu64.c | 8 +++---
> >> target/arm/helper.c | 6 +++--
> >> target/arm/hvf/hvf.c | 3 ++-
> >> target/arm/kvm.c | 30 ++++++++++++++++++---
> >> target/arm/tcg/cpu64.c | 44 ++++++++++++++++++------------
> >> 9 files changed, 101 insertions(+), 63 deletions(-)
> >
> >> diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
> >> index 7877a3b06a8e..e89a1105904c 100644
> >> --- a/target/arm/cpu-sysregs.h
> >> +++ b/target/arm/cpu-sysregs.h
> >> @@ -39,4 +39,8 @@ extern const uint32_t id_register_sysreg[NUM_ID_IDX];
> >>
> >> int get_sysreg_idx(ARMSysRegs sysreg);
> >>
> >> +#ifdef CONFIG_KVM
> >> +uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg);
> >> +#endif
> >
> > This breaks the build when KVM is disabled, and/or not available
> > on the build target architecture
> >
> > In file included from ../target/arm/cpu.h:35,
> > from /var/home/berrange/src/virt/qemu/include/hw/arm/digic.h:21,
> > from ../hw/arm/digic_boards.c:31:
> > /var/home/berrange/src/virt/qemu/target/arm/cpu-sysregs.h:42:8: error: attempt to use poisoned ‘CONFIG_KVM’
> > 42 | #ifdef CONFIG_KVM
> > | ^
> > In file included from /var/home/berrange/src/virt/qemu/include/exec/poison.h:7,
> > from /var/home/berrange/src/virt/qemu/include/qemu/osdep.h:38,
> > from ../hw/arm/digic_boards.c:26:
> > ./config-poison.h:185:20: note: poisoned here
> > 185 | #pragma GCC poison CONFIG_KVM
> > | ^~~~~~~~~~
> > ninja: build stopped: subcommand failed.
>
> I have already fixed that one in v6.
Ah yes, I was testing v5 as that one can apply with the KVM CPU model series
With regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o- https://fstop138.berrange.com :|
|: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH for-10.1 v5 03/13] arm/cpu: Store aa64isar1/2 into the idregs array
2025-04-09 14:42 [PATCH for-10.1 v5 00/13] arm: rework id register storage Cornelia Huck
2025-04-09 14:42 ` [PATCH for-10.1 v5 01/13] arm/cpu: Add sysreg definitions in cpu-sysregs.h Cornelia Huck
2025-04-09 14:42 ` [PATCH for-10.1 v5 02/13] arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays Cornelia Huck
@ 2025-04-09 14:42 ` Cornelia Huck
2025-04-28 15:00 ` Eric Auger
2025-04-09 14:42 ` [PATCH for-10.1 v5 04/13] arm/cpu: Store aa64pfr0/1 " Cornelia Huck
` (10 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Cornelia Huck @ 2025-04-09 14:42 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-features.h | 44 +++++++++++++++++++--------------------
target/arm/cpu.c | 12 ++++-------
target/arm/cpu.h | 2 --
target/arm/cpu64.c | 9 ++++----
target/arm/helper.c | 4 ++--
target/arm/hvf/hvf.c | 2 +-
target/arm/kvm.c | 6 ++----
target/arm/tcg/cpu64.c | 24 ++++++++++-----------
8 files changed, 48 insertions(+), 55 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 779bcd1abb36..37946d759375 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -467,17 +467,17 @@ static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR1, JSCVT) != 0;
}
static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR1, FCMA) != 0;
}
static inline bool isar_feature_aa64_xs(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, XS) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR1, XS) != 0;
}
/*
@@ -501,9 +501,9 @@ isar_feature_pauth_feature(const ARMISARegisters *id)
* Architecturally, only one of {APA,API,APA3} may be active (non-zero)
* and the other two must be zero. Thus we may avoid conditionals.
*/
- return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) |
- FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) |
- FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3));
+ return (FIELD_EX64_IDREG(id, ID_AA64ISAR1, APA) |
+ FIELD_EX64_IDREG(id, ID_AA64ISAR1, API) |
+ FIELD_EX64_IDREG(id, ID_AA64ISAR2, APA3));
}
static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
@@ -521,7 +521,7 @@ static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters *id)
* Return true if pauth is enabled with the architected QARMA5 algorithm.
* QEMU will always enable or disable both APA and GPA.
*/
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR1, APA) != 0;
}
static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id)
@@ -530,77 +530,77 @@ static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id)
* Return true if pauth is enabled with the architected QARMA3 algorithm.
* QEMU will always enable or disable both APA3 and GPA3.
*/
- return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR2, APA3) != 0;
}
static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR1, SB) != 0;
}
static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR1, SPECRES) != 0;
}
static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR1, FRINTTS) != 0;
}
static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR1, DPB) != 0;
}
static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR1, DPB) >= 2;
}
static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR1, BF16) != 0;
}
static inline bool isar_feature_aa64_ebf16(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) > 1;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR1, BF16) > 1;
}
static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR1, LRCPC) != 0;
}
static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR1, LRCPC) >= 2;
}
static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR1, I8MM) != 0;
}
static inline bool isar_feature_aa64_wfxt(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, WFXT) >= 2;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR2, WFXT) >= 2;
}
static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR2, BC) != 0;
}
static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS);
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR2, MOPS);
}
static inline bool isar_feature_aa64_rpres(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, RPRES);
+ return FIELD_EX64_IDREG(id, ID_AA64ISAR2, RPRES);
}
static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 750a4e957cb2..f8783eff1d41 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2129,9 +2129,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
uint64_t t;
uint32_t u;
- t = cpu->isar.id_aa64isar1;
- t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
- cpu->isar.id_aa64isar1 = t;
+ FIELD_DP64_IDREG(isar, ID_AA64ISAR1, JSCVT, 0);
t = cpu->isar.id_aa64pfr0;
t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
@@ -2184,11 +2182,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
SET_IDREG(isar, ID_AA64ISAR0, t);
- t = cpu->isar.id_aa64isar1;
+ t = GET_IDREG(isar, ID_AA64ISAR1);
t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0);
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0);
- cpu->isar.id_aa64isar1 = t;
+ SET_IDREG(isar, ID_AA64ISAR1, t);
t = cpu->isar.id_aa64pfr0;
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
@@ -2228,9 +2226,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
FIELD_DP64_IDREG(isar, ID_AA64ISAR0, FHM, 0);
- t = cpu->isar.id_aa64isar1;
- t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
- cpu->isar.id_aa64isar1 = t;
+ FIELD_DP64_IDREG(isar, ID_AA64ISAR1, FRINTTS, 0);
u = cpu->isar.mvfr0;
u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 57d00da0a927..4a143bc64b27 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1097,8 +1097,6 @@ struct ArchCPU {
uint32_t dbgdidr;
uint32_t dbgdevid;
uint32_t dbgdevid1;
- uint64_t id_aa64isar1;
- uint64_t id_aa64isar2;
uint64_t id_aa64pfr0;
uint64_t id_aa64pfr1;
uint64_t id_aa64mmfr0;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index c781efeb7cef..b914f2ed58b5 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -502,6 +502,7 @@ void aarch64_add_sme_properties(Object *obj)
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
{
ARMPauthFeature features = cpu_isar_feature(pauth_feature, cpu);
+ ARMISARegisters *isar = &cpu->isar;
uint64_t isar1, isar2;
/*
@@ -512,13 +513,13 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
*
* Begin by disabling all fields.
*/
- isar1 = cpu->isar.id_aa64isar1;
+ isar1 = GET_IDREG(isar, ID_AA64ISAR1);
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, 0);
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 0);
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, 0);
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 0);
- isar2 = cpu->isar.id_aa64isar2;
+ isar2 = GET_IDREG(isar, ID_AA64ISAR2);
isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0);
isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0);
@@ -580,8 +581,8 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
}
}
- cpu->isar.id_aa64isar1 = isar1;
- cpu->isar.id_aa64isar2 = isar2;
+ SET_IDREG(isar, ID_AA64ISAR1, isar1);
+ SET_IDREG(isar, ID_AA64ISAR2, isar2);
}
static const Property arm_cpu_pauth_property =
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8062e5190425..548e51e82a8e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8006,12 +8006,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64isar1 },
+ .resetvalue = GET_IDREG(isar, ID_AA64ISAR1)},
{ .name = "ID_AA64ISAR2_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64isar2 },
+ .resetvalue = GET_IDREG(isar, ID_AA64ISAR2)},
{ .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 0213702ef094..8d6852fd7a52 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -867,7 +867,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
{ HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 },
{ HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },
{ HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] },
- { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 },
+ { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_IDX] },
/* Add ID_AA64ISAR2_EL1 here when HVF supports it */
{ HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
{ HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index d187df80f077..e8992348b27f 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -362,10 +362,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1,
ARM64_SYS_REG(3, 0, 0, 5, 1));
err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX);
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
- ARM64_SYS_REG(3, 0, 0, 6, 1));
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2,
- ARM64_SYS_REG(3, 0, 0, 6, 2));
+ err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR1_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR2_EL1_IDX);
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0,
ARM64_SYS_REG(3, 0, 0, 7, 0));
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index f31bb9ceaac9..f62e62595d8b 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -68,7 +68,7 @@ static void aarch64_a35_initfn(Object *obj)
cpu->isar.id_aa64dfr0 = 0x10305106;
cpu->isar.id_aa64dfr1 = 0;
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
- cpu->isar.id_aa64isar1 = 0;
+ SET_IDREG(isar, ID_AA64ISAR1, 0);
cpu->isar.id_aa64mmfr0 = 0x00101122;
cpu->isar.id_aa64mmfr1 = 0;
cpu->clidr = 0x0a200023;
@@ -224,7 +224,7 @@ static void aarch64_a55_initfn(Object *obj)
cpu->dcz_blocksize = 4; /* 64 bytes */
cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+ SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
@@ -357,7 +357,7 @@ static void aarch64_a76_initfn(Object *obj)
cpu->dcz_blocksize = 4;
cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+ SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
@@ -437,7 +437,7 @@ static void aarch64_a64fx_initfn(Object *obj)
cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
SET_IDREG(isar, ID_AA64ISAR0, 0x0000000010211120);
- cpu->isar.id_aa64isar1 = 0x0000000000010001;
+ SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000010001);
SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000);
cpu->clidr = 0x0000000080000023;
/* 64KB L1 dcache */
@@ -605,7 +605,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
cpu->dcz_blocksize = 4;
cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+ SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
@@ -684,7 +684,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->isar.id_aa64dfr0 = 0x000001f210305519ull;
cpu->isar.id_aa64dfr1 = 0x00000000;
SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */
- cpu->isar.id_aa64isar1 = 0x0011100001211032ull;
+ SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull);
cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull;
@@ -933,7 +933,7 @@ static void aarch64_a710_initfn(Object *obj)
cpu->id_aa64afr0 = 0;
cpu->id_aa64afr1 = 0;
SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */
- cpu->isar.id_aa64isar1 = 0x0010111101211052ull;
+ SET_IDREG(isar, ID_AA64ISAR1, 0x0010111101211052ull);
cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull;
@@ -1035,7 +1035,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->id_aa64afr0 = 0;
cpu->id_aa64afr1 = 0;
SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto and FEAT_RNG */
- cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
+ SET_IDREG(isar, ID_AA64ISAR1, 0x0011111101211052ull);
cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x1221011112101011ull;
@@ -1160,7 +1160,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
SET_IDREG(isar, ID_AA64ISAR0, t);
- t = cpu->isar.id_aa64isar1;
+ t = GET_IDREG(isar, ID_AA64ISAR1);
t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED);
t = FIELD_DP64(t, ID_AA64ISAR1, API, 1);
@@ -1174,14 +1174,14 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
t = FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */
- cpu->isar.id_aa64isar1 = t;
+ SET_IDREG(isar, ID_AA64ISAR1, t);
- t = cpu->isar.id_aa64isar2;
+ t = GET_IDREG(isar, ID_AA64ISAR2);
t = FIELD_DP64(t, ID_AA64ISAR2, RPRES, 1); /* FEAT_RPRES */
t = FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */
t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */
t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */
- cpu->isar.id_aa64isar2 = t;
+ SET_IDREG(isar, ID_AA64ISAR2, t);
t = cpu->isar.id_aa64pfr0;
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH for-10.1 v5 03/13] arm/cpu: Store aa64isar1/2 into the idregs array
2025-04-09 14:42 ` [PATCH for-10.1 v5 03/13] arm/cpu: Store aa64isar1/2 into the idregs array Cornelia Huck
@ 2025-04-28 15:00 ` Eric Auger
0 siblings, 0 replies; 29+ messages in thread
From: Eric Auger @ 2025-04-28 15:00 UTC (permalink / raw)
To: Cornelia Huck, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini
On 4/9/25 4:42 PM, Cornelia Huck wrote:
> From: Eric Auger <eric.auger@redhat.com>
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Sebastian Ott <sebott@redhat.com>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
> ---
> target/arm/cpu-features.h | 44 +++++++++++++++++++--------------------
> target/arm/cpu.c | 12 ++++-------
> target/arm/cpu.h | 2 --
> target/arm/cpu64.c | 9 ++++----
> target/arm/helper.c | 4 ++--
> target/arm/hvf/hvf.c | 2 +-
> target/arm/kvm.c | 6 ++----
> target/arm/tcg/cpu64.c | 24 ++++++++++-----------
> 8 files changed, 48 insertions(+), 55 deletions(-)
>
> diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
> index 779bcd1abb36..37946d759375 100644
> --- a/target/arm/cpu-features.h
> +++ b/target/arm/cpu-features.h
> @@ -467,17 +467,17 @@ static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
>
> static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, JSCVT) != 0;
> }
>
> static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, FCMA) != 0;
> }
>
> static inline bool isar_feature_aa64_xs(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, XS) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, XS) != 0;
> }
>
> /*
> @@ -501,9 +501,9 @@ isar_feature_pauth_feature(const ARMISARegisters *id)
> * Architecturally, only one of {APA,API,APA3} may be active (non-zero)
> * and the other two must be zero. Thus we may avoid conditionals.
> */
> - return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) |
> - FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) |
> - FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3));
> + return (FIELD_EX64_IDREG(id, ID_AA64ISAR1, APA) |
> + FIELD_EX64_IDREG(id, ID_AA64ISAR1, API) |
> + FIELD_EX64_IDREG(id, ID_AA64ISAR2, APA3));
> }
>
> static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
> @@ -521,7 +521,7 @@ static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters *id)
> * Return true if pauth is enabled with the architected QARMA5 algorithm.
> * QEMU will always enable or disable both APA and GPA.
> */
> - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, APA) != 0;
> }
>
> static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id)
> @@ -530,77 +530,77 @@ static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id)
> * Return true if pauth is enabled with the architected QARMA3 algorithm.
> * QEMU will always enable or disable both APA3 and GPA3.
> */
> - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, APA3) != 0;
> }
>
> static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, SB) != 0;
> }
>
> static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, SPECRES) != 0;
> }
>
> static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, FRINTTS) != 0;
> }
>
> static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, DPB) != 0;
> }
>
> static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, DPB) >= 2;
> }
>
> static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, BF16) != 0;
> }
>
> static inline bool isar_feature_aa64_ebf16(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) > 1;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, BF16) > 1;
> }
>
> static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, LRCPC) != 0;
> }
>
> static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, LRCPC) >= 2;
> }
>
> static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR1, I8MM) != 0;
> }
>
> static inline bool isar_feature_aa64_wfxt(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, WFXT) >= 2;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, WFXT) >= 2;
> }
>
> static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, BC) != 0;
> }
>
> static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS);
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, MOPS);
> }
>
> static inline bool isar_feature_aa64_rpres(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, RPRES);
> + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, RPRES);
> }
>
> static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 750a4e957cb2..f8783eff1d41 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2129,9 +2129,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> uint64_t t;
> uint32_t u;
>
> - t = cpu->isar.id_aa64isar1;
> - t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
> - cpu->isar.id_aa64isar1 = t;
> + FIELD_DP64_IDREG(isar, ID_AA64ISAR1, JSCVT, 0);
>
> t = cpu->isar.id_aa64pfr0;
> t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
> @@ -2184,11 +2182,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
> SET_IDREG(isar, ID_AA64ISAR0, t);
>
> - t = cpu->isar.id_aa64isar1;
> + t = GET_IDREG(isar, ID_AA64ISAR1);
> t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
> t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0);
> t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0);
> - cpu->isar.id_aa64isar1 = t;
> + SET_IDREG(isar, ID_AA64ISAR1, t);
>
> t = cpu->isar.id_aa64pfr0;
> t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
> @@ -2228,9 +2226,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
>
> FIELD_DP64_IDREG(isar, ID_AA64ISAR0, FHM, 0);
>
> - t = cpu->isar.id_aa64isar1;
> - t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
> - cpu->isar.id_aa64isar1 = t;
> + FIELD_DP64_IDREG(isar, ID_AA64ISAR1, FRINTTS, 0);
>
> u = cpu->isar.mvfr0;
> u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 57d00da0a927..4a143bc64b27 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1097,8 +1097,6 @@ struct ArchCPU {
> uint32_t dbgdidr;
> uint32_t dbgdevid;
> uint32_t dbgdevid1;
> - uint64_t id_aa64isar1;
> - uint64_t id_aa64isar2;
> uint64_t id_aa64pfr0;
> uint64_t id_aa64pfr1;
> uint64_t id_aa64mmfr0;
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index c781efeb7cef..b914f2ed58b5 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -502,6 +502,7 @@ void aarch64_add_sme_properties(Object *obj)
> void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
> {
> ARMPauthFeature features = cpu_isar_feature(pauth_feature, cpu);
> + ARMISARegisters *isar = &cpu->isar;
> uint64_t isar1, isar2;
>
> /*
> @@ -512,13 +513,13 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
> *
> * Begin by disabling all fields.
> */
> - isar1 = cpu->isar.id_aa64isar1;
> + isar1 = GET_IDREG(isar, ID_AA64ISAR1);
> isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, 0);
> isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 0);
> isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, 0);
> isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 0);
>
> - isar2 = cpu->isar.id_aa64isar2;
> + isar2 = GET_IDREG(isar, ID_AA64ISAR2);
> isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0);
> isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0);
>
> @@ -580,8 +581,8 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
> }
> }
>
> - cpu->isar.id_aa64isar1 = isar1;
> - cpu->isar.id_aa64isar2 = isar2;
> + SET_IDREG(isar, ID_AA64ISAR1, isar1);
> + SET_IDREG(isar, ID_AA64ISAR2, isar2);
> }
>
> static const Property arm_cpu_pauth_property =
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 8062e5190425..548e51e82a8e 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -8006,12 +8006,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa64_tid3,
> - .resetvalue = cpu->isar.id_aa64isar1 },
> + .resetvalue = GET_IDREG(isar, ID_AA64ISAR1)},
> { .name = "ID_AA64ISAR2_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa64_tid3,
> - .resetvalue = cpu->isar.id_aa64isar2 },
> + .resetvalue = GET_IDREG(isar, ID_AA64ISAR2)},
> { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
> .access = PL1_R, .type = ARM_CP_CONST,
> diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
> index 0213702ef094..8d6852fd7a52 100644
> --- a/target/arm/hvf/hvf.c
> +++ b/target/arm/hvf/hvf.c
> @@ -867,7 +867,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 },
> { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },
> { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] },
> - { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 },
> + { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_IDX] },
> /* Add ID_AA64ISAR2_EL1 here when HVF supports it */
> { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
> { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
> diff --git a/target/arm/kvm.c b/target/arm/kvm.c
> index d187df80f077..e8992348b27f 100644
> --- a/target/arm/kvm.c
> +++ b/target/arm/kvm.c
> @@ -362,10 +362,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1,
> ARM64_SYS_REG(3, 0, 0, 5, 1));
> err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX);
> - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
> - ARM64_SYS_REG(3, 0, 0, 6, 1));
> - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2,
> - ARM64_SYS_REG(3, 0, 0, 6, 2));
> + err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR1_EL1_IDX);
> + err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR2_EL1_IDX);
> err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0,
> ARM64_SYS_REG(3, 0, 0, 7, 0));
> err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,
Nit: same here. Later you might send a simplification patch doing
s/fdarray[2]/fd
Otherwise looks good after another reading
Eric
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index f31bb9ceaac9..f62e62595d8b 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -68,7 +68,7 @@ static void aarch64_a35_initfn(Object *obj)
> cpu->isar.id_aa64dfr0 = 0x10305106;
> cpu->isar.id_aa64dfr1 = 0;
> SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> - cpu->isar.id_aa64isar1 = 0;
> + SET_IDREG(isar, ID_AA64ISAR1, 0);
> cpu->isar.id_aa64mmfr0 = 0x00101122;
> cpu->isar.id_aa64mmfr1 = 0;
> cpu->clidr = 0x0a200023;
> @@ -224,7 +224,7 @@ static void aarch64_a55_initfn(Object *obj)
> cpu->dcz_blocksize = 4; /* 64 bytes */
> cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
> SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
> - cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
> + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
> cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
> @@ -357,7 +357,7 @@ static void aarch64_a76_initfn(Object *obj)
> cpu->dcz_blocksize = 4;
> cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
> SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
> - cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
> + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
> cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
> @@ -437,7 +437,7 @@ static void aarch64_a64fx_initfn(Object *obj)
> cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
> cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
> SET_IDREG(isar, ID_AA64ISAR0, 0x0000000010211120);
> - cpu->isar.id_aa64isar1 = 0x0000000000010001;
> + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000010001);
> SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000);
> cpu->clidr = 0x0000000080000023;
> /* 64KB L1 dcache */
> @@ -605,7 +605,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
> cpu->dcz_blocksize = 4;
> cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
> SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
> - cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
> + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
> cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
> @@ -684,7 +684,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
> cpu->isar.id_aa64dfr0 = 0x000001f210305519ull;
> cpu->isar.id_aa64dfr1 = 0x00000000;
> SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */
> - cpu->isar.id_aa64isar1 = 0x0011100001211032ull;
> + SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull);
> cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull;
> @@ -933,7 +933,7 @@ static void aarch64_a710_initfn(Object *obj)
> cpu->id_aa64afr0 = 0;
> cpu->id_aa64afr1 = 0;
> SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */
> - cpu->isar.id_aa64isar1 = 0x0010111101211052ull;
> + SET_IDREG(isar, ID_AA64ISAR1, 0x0010111101211052ull);
> cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull;
> @@ -1035,7 +1035,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
> cpu->id_aa64afr0 = 0;
> cpu->id_aa64afr1 = 0;
> SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto and FEAT_RNG */
> - cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
> + SET_IDREG(isar, ID_AA64ISAR1, 0x0011111101211052ull);
> cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> cpu->isar.id_aa64mmfr2 = 0x1221011112101011ull;
> @@ -1160,7 +1160,7 @@ void aarch64_max_tcg_initfn(Object *obj)
> t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
> SET_IDREG(isar, ID_AA64ISAR0, t);
>
> - t = cpu->isar.id_aa64isar1;
> + t = GET_IDREG(isar, ID_AA64ISAR1);
> t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
> t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED);
> t = FIELD_DP64(t, ID_AA64ISAR1, API, 1);
> @@ -1174,14 +1174,14 @@ void aarch64_max_tcg_initfn(Object *obj)
> t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
> t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
> t = FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */
> - cpu->isar.id_aa64isar1 = t;
> + SET_IDREG(isar, ID_AA64ISAR1, t);
>
> - t = cpu->isar.id_aa64isar2;
> + t = GET_IDREG(isar, ID_AA64ISAR2);
> t = FIELD_DP64(t, ID_AA64ISAR2, RPRES, 1); /* FEAT_RPRES */
> t = FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */
> t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */
> t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */
> - cpu->isar.id_aa64isar2 = t;
> + SET_IDREG(isar, ID_AA64ISAR2, t);
>
> t = cpu->isar.id_aa64pfr0;
> t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH for-10.1 v5 04/13] arm/cpu: Store aa64pfr0/1 into the idregs array
2025-04-09 14:42 [PATCH for-10.1 v5 00/13] arm: rework id register storage Cornelia Huck
` (2 preceding siblings ...)
2025-04-09 14:42 ` [PATCH for-10.1 v5 03/13] arm/cpu: Store aa64isar1/2 into the idregs array Cornelia Huck
@ 2025-04-09 14:42 ` Cornelia Huck
2025-04-28 15:39 ` Eric Auger
2025-04-09 14:42 ` [PATCH for-10.1 v5 05/13] arm/cpu: Store aa64mmfr0-3 " Cornelia Huck
` (9 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Cornelia Huck @ 2025-04-09 14:42 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-features.h | 40 ++++++++++++++++-----------------
target/arm/cpu.c | 29 ++++++++----------------
target/arm/cpu.h | 2 --
target/arm/cpu64.c | 14 ++++--------
target/arm/helper.c | 6 ++---
target/arm/hvf/hvf.c | 9 ++++----
target/arm/kvm.c | 24 +++++++++-----------
target/arm/tcg/cpu64.c | 47 ++++++++++++++++++---------------------
8 files changed, 73 insertions(+), 98 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 37946d759375..5cc4721e6406 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -606,68 +606,68 @@ static inline bool isar_feature_aa64_rpres(const ARMISARegisters *id)
static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
{
/* We always set the AdvSIMD and FP fields identically. */
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR0, FP) != 0xf;
}
static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
{
/* We always set the AdvSIMD and FP fields identically wrt FP16. */
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR0, FP) == 1;
}
static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL0) >= 2;
}
static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL1) >= 2;
}
static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL2) >= 2;
}
static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) != 0;
}
static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) >= 2;
}
static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR0, SVE) != 0;
}
static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR0, SEL2) != 0;
}
static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR0, RME) != 0;
}
static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR0, DIT) != 0;
}
static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
{
- int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
+ int key = FIELD_EX64_IDREG(id, ID_AA64PFR0, CSV2);
if (key >= 2) {
return true; /* FEAT_CSV2_2 */
}
if (key == 1) {
- key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
+ key = FIELD_EX64_IDREG(id, ID_AA64PFR1, CSV2_FRAC);
return key >= 2; /* FEAT_CSV2_1p2 */
}
return false;
@@ -675,37 +675,37 @@ static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR1, SSBS) != 0;
}
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR1, BT) != 0;
}
static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) != 0;
}
static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) >= 2;
}
static inline bool isar_feature_aa64_mte3(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 3;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) >= 3;
}
static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR1, SME) != 0;
}
static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, NMI) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64PFR1, NMI) != 0;
}
static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f8783eff1d41..23be9ab97334 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2126,14 +2126,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
}
if (!cpu->has_vfp) {
- uint64_t t;
uint32_t u;
FIELD_DP64_IDREG(isar, ID_AA64ISAR1, JSCVT, 0);
- t = cpu->isar.id_aa64pfr0;
- t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
- cpu->isar.id_aa64pfr0 = t;
+ FIELD_DP64_IDREG(isar, ID_AA64PFR0, FP, 0xf);
u = cpu->isar.id_isar6;
u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
@@ -2188,9 +2185,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0);
SET_IDREG(isar, ID_AA64ISAR1, t);
- t = cpu->isar.id_aa64pfr0;
- t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
- cpu->isar.id_aa64pfr0 = t;
+ FIELD_DP64_IDREG(isar, ID_AA64PFR0, ADVSIMD, 0xf);
u = cpu->isar.id_isar5;
u = FIELD_DP32(u, ID_ISAR5, AES, 0);
@@ -2332,12 +2327,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
*/
cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
- cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
- ID_AA64PFR0, EL3, 0);
+ FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0);
/* Disable the realm management extension, which requires EL3. */
- cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
- ID_AA64PFR0, RME, 0);
+ FIELD_DP64_IDREG(isar, ID_AA64PFR0, RME, 0);
}
if (!cpu->has_el2) {
@@ -2372,8 +2365,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* Disable the hypervisor feature bits in the processor feature
* registers if we don't have EL2.
*/
- cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
- ID_AA64PFR0, EL2, 0);
+ FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 0);
cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
ID_PFR1, VIRTUALIZATION, 0);
}
@@ -2394,8 +2386,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* This matches Cortex-A710 BROADCASTMTE input being LOW.
*/
if (tcg_enabled() && cpu->tag_memory == NULL) {
- cpu->isar.id_aa64pfr1 =
- FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
+ FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 1);
}
/*
@@ -2403,7 +2394,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* enabled on the guest (i.e mte=off), clear guest's MTE bits."
*/
if (kvm_enabled() && !cpu->kvm_mte) {
- FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+ FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 0);
}
#endif
}
@@ -2442,13 +2433,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
cpu->isar.id_dfr0 =
FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0);
/* FEAT_AMU (Activity Monitors Extension) */
- cpu->isar.id_aa64pfr0 =
- FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0);
+ FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0);
cpu->isar.id_pfr0 =
FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0);
/* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
- cpu->isar.id_aa64pfr0 =
- FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0);
+ FIELD_DP64_IDREG(isar, ID_AA64PFR0, MPAM, 0);
}
/* MPU can be configured out of a PMSA CPU either by setting has-mpu
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 4a143bc64b27..83ac125b97c5 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1097,8 +1097,6 @@ struct ArchCPU {
uint32_t dbgdidr;
uint32_t dbgdevid;
uint32_t dbgdevid1;
- uint64_t id_aa64pfr0;
- uint64_t id_aa64pfr1;
uint64_t id_aa64mmfr0;
uint64_t id_aa64mmfr1;
uint64_t id_aa64mmfr2;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index b914f2ed58b5..111b2514218e 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -310,16 +310,13 @@ static bool cpu_arm_get_sve(Object *obj, Error **errp)
static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
- uint64_t t;
if (value && kvm_enabled() && !kvm_arm_sve_supported()) {
error_setg(errp, "'sve' feature not supported by KVM on this host");
return;
}
- t = cpu->isar.id_aa64pfr0;
- t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
- cpu->isar.id_aa64pfr0 = t;
+ FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, SVE, value);
}
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
@@ -370,11 +367,8 @@ static bool cpu_arm_get_sme(Object *obj, Error **errp)
static void cpu_arm_set_sme(Object *obj, bool value, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
- uint64_t t;
- t = cpu->isar.id_aa64pfr1;
- t = FIELD_DP64(t, ID_AA64PFR1, SME, value);
- cpu->isar.id_aa64pfr1 = t;
+ FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, value);
}
static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp)
@@ -676,7 +670,7 @@ static void aarch64_a57_initfn(Object *obj)
cpu->isar.id_isar4 = 0x00011142;
cpu->isar.id_isar5 = 0x00011121;
cpu->isar.id_isar6 = 0;
- cpu->isar.id_aa64pfr0 = 0x00002222;
+ SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
cpu->isar.id_aa64dfr0 = 0x10305106;
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
cpu->isar.id_aa64mmfr0 = 0x00001124;
@@ -738,7 +732,7 @@ static void aarch64_a53_initfn(Object *obj)
cpu->isar.id_isar4 = 0x00011142;
cpu->isar.id_isar5 = 0x00011121;
cpu->isar.id_isar6 = 0;
- cpu->isar.id_aa64pfr0 = 0x00002222;
+ SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
cpu->isar.id_aa64dfr0 = 0x10305106;
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 548e51e82a8e..716d0570f6d6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6940,7 +6940,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = env_archcpu(env);
- uint64_t pfr0 = cpu->isar.id_aa64pfr0;
+ uint64_t pfr0 = GET_IDREG(&cpu->isar, ID_AA64PFR0);
if (env->gicv3state) {
pfr0 |= 1 << 24;
@@ -7914,7 +7914,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL1_R,
#ifdef CONFIG_USER_ONLY
.type = ARM_CP_CONST,
- .resetvalue = cpu->isar.id_aa64pfr0
+ .resetvalue = GET_IDREG(isar, ID_AA64PFR0)
#else
.type = ARM_CP_NO_RAW,
.accessfn = access_aa64_tid3,
@@ -7926,7 +7926,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64pfr1},
+ .resetvalue = GET_IDREG(isar, ID_AA64PFR1)},
{ .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 8d6852fd7a52..9d37ca6bbbde 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -862,8 +862,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
int reg;
uint64_t *val;
} regs[] = {
- { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 },
- { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 },
+ { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_IDX] },
+ { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_IDX] },
{ HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 },
{ HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },
{ HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] },
@@ -910,7 +910,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* - fix any assumptions we made that SME implies SVE (since
* on the M4 there is SME but not SVE)
*/
- host_isar.id_aa64pfr1 &= ~R_ID_AA64PFR1_SME_MASK;
+ SET_IDREG(&host_isar, ID_AA64PFR1,
+ GET_IDREG(&host_isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MASK);
ahcf->isar = host_isar;
@@ -927,7 +928,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ahcf->reset_sctlr |= 0x00800000;
/* Make sure we don't advertise AArch32 support for EL0/EL1 */
- if ((host_isar.id_aa64pfr0 & 0xff) != 0x11) {
+ if ((GET_IDREG(&host_isar, ID_AA64PFR0) & 0xff) != 0x11) {
return false;
}
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index e8992348b27f..44a5e219b051 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -331,8 +331,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ahcf->dtb_compatible = "arm,arm-v8";
int fd = fdarray[2];
- err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
- ARM64_SYS_REG(3, 0, 0, 4, 0));
+ err = get_host_cpu_reg(fd, ahcf, ID_AA64PFR0_EL1_IDX);
if (unlikely(err < 0)) {
/*
* Before v4.15, the kernel only exposed a limited number of system
@@ -350,11 +349,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* ??? Either of these sounds like too much effort just
* to work around running a modern host kernel.
*/
- ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */
+ SET_IDREG(&ahcf->isar, ID_AA64PFR0, 0x00000011); /* EL1&0, AArch64 only */
err = 0;
} else {
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1,
- ARM64_SYS_REG(3, 0, 0, 4, 1));
+ err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX);
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0,
ARM64_SYS_REG(3, 0, 0, 4, 5));
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0,
@@ -380,10 +378,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* than skipping the reads and leaving 0, as we must avoid
* considering the values in every case.
*/
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0,
- ARM64_SYS_REG(3, 0, 0, 1, 0));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
- ARM64_SYS_REG(3, 0, 0, 1, 1));
+ err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR0_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX);
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
ARM64_SYS_REG(3, 0, 0, 1, 2));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
@@ -434,14 +430,14 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* arch/arm64/kvm/sys_regs.c:trap_dbgidr() does.
* We only do this if the CPU supports AArch32 at EL1.
*/
- if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) {
- int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS);
- int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS);
+ if (FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL1) >= 2) {
+ int wrps = FIELD_EX64(&ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS);
+ int brps = FIELD_EX64(&ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS);
int ctx_cmps =
- FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS);
+ FIELD_EX64(&ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS);
int version = 6; /* ARMv8 debug architecture */
bool has_el3 =
- !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3);
+ !!FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL3);
uint32_t dbgdidr = 0;
dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps);
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index f62e62595d8b..478ef839bafa 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -63,8 +63,8 @@ static void aarch64_a35_initfn(Object *obj)
cpu->isar.id_isar3 = 0x01112131;
cpu->isar.id_isar4 = 0x00011142;
cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_aa64pfr0 = 0x00002222;
- cpu->isar.id_aa64pfr1 = 0;
+ SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
+ SET_IDREG(isar, ID_AA64PFR1, 0);
cpu->isar.id_aa64dfr0 = 0x10305106;
cpu->isar.id_aa64dfr1 = 0;
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
@@ -158,11 +158,8 @@ static bool cpu_arm_get_rme(Object *obj, Error **errp)
static void cpu_arm_set_rme(Object *obj, bool value, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
- uint64_t t;
- t = cpu->isar.id_aa64pfr0;
- t = FIELD_DP64(t, ID_AA64PFR0, RME, value);
- cpu->isar.id_aa64pfr0 = t;
+ FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, RME, value);
}
static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name,
@@ -228,8 +225,8 @@ static void aarch64_a55_initfn(Object *obj)
cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
- cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
- cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
+ SET_IDREG(isar, ID_AA64PFR0, 0x0000000010112222ull);
+ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x04010088;
cpu->isar.id_isar0 = 0x02101110;
@@ -312,7 +309,7 @@ static void aarch64_a72_initfn(Object *obj)
cpu->isar.id_isar3 = 0x01112131;
cpu->isar.id_isar4 = 0x00011142;
cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_aa64pfr0 = 0x00002222;
+ SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
cpu->isar.id_aa64dfr0 = 0x10305106;
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
cpu->isar.id_aa64mmfr0 = 0x00001124;
@@ -361,8 +358,8 @@ static void aarch64_a76_initfn(Object *obj)
cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
+ SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
+ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x04010088;
cpu->isar.id_isar0 = 0x02101110;
@@ -427,8 +424,8 @@ static void aarch64_a64fx_initfn(Object *obj)
cpu->revidr = 0x00000000;
cpu->ctr = 0x86668006;
cpu->reset_sctlr = 0x30000180;
- cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
- cpu->isar.id_aa64pfr1 = 0x0000000000000000;
+ SET_IDREG(isar, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions */
+ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000);
cpu->isar.id_aa64dfr0 = 0x0000000010305408;
cpu->isar.id_aa64dfr1 = 0x0000000000000000;
cpu->id_aa64afr0 = 0x0000000000000000;
@@ -609,8 +606,8 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
+ SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
+ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x04010088;
cpu->isar.id_isar0 = 0x02101110;
@@ -688,8 +685,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull;
- cpu->isar.id_aa64pfr0 = 0x1101110120111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
+ SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in later */
+ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x15011099;
cpu->isar.id_isar0 = 0x02101110;
@@ -925,8 +922,8 @@ static void aarch64_a710_initfn(Object *obj)
cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043;
cpu->isar.id_pfr2 = 0x00000011;
- cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
+ SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
+ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull);
SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
cpu->isar.id_aa64dfr0 = 0x000011f010305619ull;
cpu->isar.id_aa64dfr1 = 0;
@@ -1027,8 +1024,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043;
cpu->isar.id_pfr2 = 0x00000011;
- cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
+ SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
+ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull);
SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
cpu->isar.id_aa64dfr0 = 0x000011f210305619ull;
cpu->isar.id_aa64dfr1 = 0;
@@ -1183,7 +1180,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */
SET_IDREG(isar, ID_AA64ISAR2, t);
- t = cpu->isar.id_aa64pfr0;
+ t = GET_IDREG(isar, ID_AA64PFR0);
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */
@@ -1192,9 +1189,9 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */
t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
- cpu->isar.id_aa64pfr0 = t;
+ SET_IDREG(isar, ID_AA64PFR0, t);
- t = cpu->isar.id_aa64pfr1;
+ t = GET_IDREG(isar, ID_AA64PFR1);
t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
/*
@@ -1207,7 +1204,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */
t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */
- cpu->isar.id_aa64pfr1 = t;
+ SET_IDREG(isar, ID_AA64PFR1, t);
t = cpu->isar.id_aa64mmfr0;
t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH for-10.1 v5 04/13] arm/cpu: Store aa64pfr0/1 into the idregs array
2025-04-09 14:42 ` [PATCH for-10.1 v5 04/13] arm/cpu: Store aa64pfr0/1 " Cornelia Huck
@ 2025-04-28 15:39 ` Eric Auger
2025-04-29 9:38 ` Cornelia Huck
0 siblings, 1 reply; 29+ messages in thread
From: Eric Auger @ 2025-04-28 15:39 UTC (permalink / raw)
To: Cornelia Huck, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini
On 4/9/25 4:42 PM, Cornelia Huck wrote:
> From: Eric Auger <eric.auger@redhat.com>
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Sebastian Ott <sebott@redhat.com>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
> ---
> target/arm/cpu-features.h | 40 ++++++++++++++++-----------------
> target/arm/cpu.c | 29 ++++++++----------------
> target/arm/cpu.h | 2 --
> target/arm/cpu64.c | 14 ++++--------
> target/arm/helper.c | 6 ++---
> target/arm/hvf/hvf.c | 9 ++++----
> target/arm/kvm.c | 24 +++++++++-----------
> target/arm/tcg/cpu64.c | 47 ++++++++++++++++++---------------------
> 8 files changed, 73 insertions(+), 98 deletions(-)
>
> diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
> index 37946d759375..5cc4721e6406 100644
> --- a/target/arm/cpu-features.h
> +++ b/target/arm/cpu-features.h
> @@ -606,68 +606,68 @@ static inline bool isar_feature_aa64_rpres(const ARMISARegisters *id)
> static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
> {
> /* We always set the AdvSIMD and FP fields identically. */
> - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR0, FP) != 0xf;
> }
>
> static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
> {
> /* We always set the AdvSIMD and FP fields identically wrt FP16. */
> - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR0, FP) == 1;
> }
>
> static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL0) >= 2;
> }
>
> static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL1) >= 2;
> }
>
> static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR0, EL2) >= 2;
> }
>
> static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) != 0;
> }
>
> static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR0, RAS) >= 2;
> }
>
> static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR0, SVE) != 0;
> }
>
> static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR0, SEL2) != 0;
> }
>
> static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR0, RME) != 0;
> }
>
> static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR0, DIT) != 0;
> }
>
> static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
> {
> - int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
> + int key = FIELD_EX64_IDREG(id, ID_AA64PFR0, CSV2);
> if (key >= 2) {
> return true; /* FEAT_CSV2_2 */
> }
> if (key == 1) {
> - key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
> + key = FIELD_EX64_IDREG(id, ID_AA64PFR1, CSV2_FRAC);
> return key >= 2; /* FEAT_CSV2_1p2 */
> }
> return false;
> @@ -675,37 +675,37 @@ static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
>
> static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR1, SSBS) != 0;
> }
>
> static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR1, BT) != 0;
> }
>
> static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) != 0;
> }
>
> static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) >= 2;
> }
>
> static inline bool isar_feature_aa64_mte3(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 3;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR1, MTE) >= 3;
> }
>
> static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR1, SME) != 0;
> }
>
> static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, NMI) != 0;
> + return FIELD_EX64_IDREG(id, ID_AA64PFR1, NMI) != 0;
> }
>
> static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index f8783eff1d41..23be9ab97334 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2126,14 +2126,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> }
>
> if (!cpu->has_vfp) {
> - uint64_t t;
> uint32_t u;
>
> FIELD_DP64_IDREG(isar, ID_AA64ISAR1, JSCVT, 0);
>
> - t = cpu->isar.id_aa64pfr0;
> - t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
> - cpu->isar.id_aa64pfr0 = t;
> + FIELD_DP64_IDREG(isar, ID_AA64PFR0, FP, 0xf);
>
> u = cpu->isar.id_isar6;
> u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
> @@ -2188,9 +2185,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0);
> SET_IDREG(isar, ID_AA64ISAR1, t);
>
> - t = cpu->isar.id_aa64pfr0;
> - t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
> - cpu->isar.id_aa64pfr0 = t;
> + FIELD_DP64_IDREG(isar, ID_AA64PFR0, ADVSIMD, 0xf);
>
> u = cpu->isar.id_isar5;
> u = FIELD_DP32(u, ID_ISAR5, AES, 0);
> @@ -2332,12 +2327,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> */
> cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
> cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
> - cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
> - ID_AA64PFR0, EL3, 0);
> + FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0);
>
> /* Disable the realm management extension, which requires EL3. */
> - cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
> - ID_AA64PFR0, RME, 0);
> + FIELD_DP64_IDREG(isar, ID_AA64PFR0, RME, 0);
> }
>
> if (!cpu->has_el2) {
> @@ -2372,8 +2365,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> * Disable the hypervisor feature bits in the processor feature
> * registers if we don't have EL2.
> */
> - cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
> - ID_AA64PFR0, EL2, 0);
> + FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 0);
> cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
> ID_PFR1, VIRTUALIZATION, 0);
> }
> @@ -2394,8 +2386,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> * This matches Cortex-A710 BROADCASTMTE input being LOW.
> */
> if (tcg_enabled() && cpu->tag_memory == NULL) {
> - cpu->isar.id_aa64pfr1 =
> - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
> + FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 1);
> }
>
> /*
> @@ -2403,7 +2394,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> * enabled on the guest (i.e mte=off), clear guest's MTE bits."
> */
> if (kvm_enabled() && !cpu->kvm_mte) {
> - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
> + FIELD_DP64_IDREG(isar, ID_AA64PFR1, MTE, 0);
> }
> #endif
> }
> @@ -2442,13 +2433,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> cpu->isar.id_dfr0 =
> FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0);
> /* FEAT_AMU (Activity Monitors Extension) */
> - cpu->isar.id_aa64pfr0 =
> - FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0);
> + FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0);
> cpu->isar.id_pfr0 =
> FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0);
> /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
> - cpu->isar.id_aa64pfr0 =
> - FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0);
> + FIELD_DP64_IDREG(isar, ID_AA64PFR0, MPAM, 0);
> }
>
> /* MPU can be configured out of a PMSA CPU either by setting has-mpu
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 4a143bc64b27..83ac125b97c5 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1097,8 +1097,6 @@ struct ArchCPU {
> uint32_t dbgdidr;
> uint32_t dbgdevid;
> uint32_t dbgdevid1;
> - uint64_t id_aa64pfr0;
> - uint64_t id_aa64pfr1;
> uint64_t id_aa64mmfr0;
> uint64_t id_aa64mmfr1;
> uint64_t id_aa64mmfr2;
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index b914f2ed58b5..111b2514218e 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -310,16 +310,13 @@ static bool cpu_arm_get_sve(Object *obj, Error **errp)
> static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> - uint64_t t;
>
> if (value && kvm_enabled() && !kvm_arm_sve_supported()) {
> error_setg(errp, "'sve' feature not supported by KVM on this host");
> return;
> }
>
> - t = cpu->isar.id_aa64pfr0;
> - t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
> - cpu->isar.id_aa64pfr0 = t;
> + FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, SVE, value);
> }
>
> void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
> @@ -370,11 +367,8 @@ static bool cpu_arm_get_sme(Object *obj, Error **errp)
> static void cpu_arm_set_sme(Object *obj, bool value, Error **errp)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> - uint64_t t;
>
> - t = cpu->isar.id_aa64pfr1;
> - t = FIELD_DP64(t, ID_AA64PFR1, SME, value);
> - cpu->isar.id_aa64pfr1 = t;
> + FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, value);
> }
>
> static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp)
> @@ -676,7 +670,7 @@ static void aarch64_a57_initfn(Object *obj)
> cpu->isar.id_isar4 = 0x00011142;
> cpu->isar.id_isar5 = 0x00011121;
> cpu->isar.id_isar6 = 0;
> - cpu->isar.id_aa64pfr0 = 0x00002222;
> + SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> cpu->isar.id_aa64dfr0 = 0x10305106;
> SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> cpu->isar.id_aa64mmfr0 = 0x00001124;
> @@ -738,7 +732,7 @@ static void aarch64_a53_initfn(Object *obj)
> cpu->isar.id_isar4 = 0x00011142;
> cpu->isar.id_isar5 = 0x00011121;
> cpu->isar.id_isar6 = 0;
> - cpu->isar.id_aa64pfr0 = 0x00002222;
> + SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> cpu->isar.id_aa64dfr0 = 0x10305106;
> SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 548e51e82a8e..716d0570f6d6 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6940,7 +6940,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
> static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
> {
> ARMCPU *cpu = env_archcpu(env);
> - uint64_t pfr0 = cpu->isar.id_aa64pfr0;
> + uint64_t pfr0 = GET_IDREG(&cpu->isar, ID_AA64PFR0);
>
> if (env->gicv3state) {
> pfr0 |= 1 << 24;
> @@ -7914,7 +7914,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .access = PL1_R,
> #ifdef CONFIG_USER_ONLY
> .type = ARM_CP_CONST,
> - .resetvalue = cpu->isar.id_aa64pfr0
> + .resetvalue = GET_IDREG(isar, ID_AA64PFR0)
> #else
> .type = ARM_CP_NO_RAW,
> .accessfn = access_aa64_tid3,
> @@ -7926,7 +7926,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa64_tid3,
> - .resetvalue = cpu->isar.id_aa64pfr1},
> + .resetvalue = GET_IDREG(isar, ID_AA64PFR1)},
> { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
> .access = PL1_R, .type = ARM_CP_CONST,
> diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
> index 8d6852fd7a52..9d37ca6bbbde 100644
> --- a/target/arm/hvf/hvf.c
> +++ b/target/arm/hvf/hvf.c
> @@ -862,8 +862,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> int reg;
> uint64_t *val;
> } regs[] = {
> - { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 },
> - { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 },
> + { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_IDX] },
> + { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_IDX] },
> { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 },
> { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },
> { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] },
> @@ -910,7 +910,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> * - fix any assumptions we made that SME implies SVE (since
> * on the M4 there is SME but not SVE)
> */
> - host_isar.id_aa64pfr1 &= ~R_ID_AA64PFR1_SME_MASK;
> + SET_IDREG(&host_isar, ID_AA64PFR1,
> + GET_IDREG(&host_isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MASK);
>
> ahcf->isar = host_isar;
>
> @@ -927,7 +928,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> ahcf->reset_sctlr |= 0x00800000;
>
> /* Make sure we don't advertise AArch32 support for EL0/EL1 */
> - if ((host_isar.id_aa64pfr0 & 0xff) != 0x11) {
> + if ((GET_IDREG(&host_isar, ID_AA64PFR0) & 0xff) != 0x11) {
> return false;
> }
>
> diff --git a/target/arm/kvm.c b/target/arm/kvm.c
> index e8992348b27f..44a5e219b051 100644
> --- a/target/arm/kvm.c
> +++ b/target/arm/kvm.c
> @@ -331,8 +331,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> ahcf->dtb_compatible = "arm,arm-v8";
> int fd = fdarray[2];
>
> - err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
> - ARM64_SYS_REG(3, 0, 0, 4, 0));
> + err = get_host_cpu_reg(fd, ahcf, ID_AA64PFR0_EL1_IDX);
> if (unlikely(err < 0)) {
> /*
> * Before v4.15, the kernel only exposed a limited number of system
> @@ -350,11 +349,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> * ??? Either of these sounds like too much effort just
> * to work around running a modern host kernel.
> */
> - ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */
> + SET_IDREG(&ahcf->isar, ID_AA64PFR0, 0x00000011); /* EL1&0, AArch64 only */
> err = 0;
> } else {
> - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1,
> - ARM64_SYS_REG(3, 0, 0, 4, 1));
> + err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX);
> err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0,
> ARM64_SYS_REG(3, 0, 0, 4, 5));
> err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0,
> @@ -380,10 +378,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> * than skipping the reads and leaving 0, as we must avoid
> * considering the values in every case.
> */
> - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0,
> - ARM64_SYS_REG(3, 0, 0, 1, 0));
> - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
> - ARM64_SYS_REG(3, 0, 0, 1, 1));
> + err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR0_EL1_IDX);
Hum I think we have a conversion mistake here:
+DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0)
+DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1)
Eric
> + err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX);
> err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
> ARM64_SYS_REG(3, 0, 0, 1, 2));
> err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
> @@ -434,14 +430,14 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does.
> * We only do this if the CPU supports AArch32 at EL1.
> */
> - if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) {
> - int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS);
> - int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS);
> + if (FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL1) >= 2) {
> + int wrps = FIELD_EX64(&ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS);
> + int brps = FIELD_EX64(&ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS);
> int ctx_cmps =
> - FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS);
> + FIELD_EX64(&ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS);
> int version = 6; /* ARMv8 debug architecture */
> bool has_el3 =
> - !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3);
> + !!FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL3);
> uint32_t dbgdidr = 0;
>
> dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps);
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index f62e62595d8b..478ef839bafa 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -63,8 +63,8 @@ static void aarch64_a35_initfn(Object *obj)
> cpu->isar.id_isar3 = 0x01112131;
> cpu->isar.id_isar4 = 0x00011142;
> cpu->isar.id_isar5 = 0x00011121;
> - cpu->isar.id_aa64pfr0 = 0x00002222;
> - cpu->isar.id_aa64pfr1 = 0;
> + SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> + SET_IDREG(isar, ID_AA64PFR1, 0);
> cpu->isar.id_aa64dfr0 = 0x10305106;
> cpu->isar.id_aa64dfr1 = 0;
> SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> @@ -158,11 +158,8 @@ static bool cpu_arm_get_rme(Object *obj, Error **errp)
> static void cpu_arm_set_rme(Object *obj, bool value, Error **errp)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> - uint64_t t;
>
> - t = cpu->isar.id_aa64pfr0;
> - t = FIELD_DP64(t, ID_AA64PFR0, RME, value);
> - cpu->isar.id_aa64pfr0 = t;
> + FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, RME, value);
> }
>
> static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name,
> @@ -228,8 +225,8 @@ static void aarch64_a55_initfn(Object *obj)
> cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
> - cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
> - cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
> + SET_IDREG(isar, ID_AA64PFR0, 0x0000000010112222ull);
> + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
> cpu->id_afr0 = 0x00000000;
> cpu->isar.id_dfr0 = 0x04010088;
> cpu->isar.id_isar0 = 0x02101110;
> @@ -312,7 +309,7 @@ static void aarch64_a72_initfn(Object *obj)
> cpu->isar.id_isar3 = 0x01112131;
> cpu->isar.id_isar4 = 0x00011142;
> cpu->isar.id_isar5 = 0x00011121;
> - cpu->isar.id_aa64pfr0 = 0x00002222;
> + SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> cpu->isar.id_aa64dfr0 = 0x10305106;
> SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> cpu->isar.id_aa64mmfr0 = 0x00001124;
> @@ -361,8 +358,8 @@ static void aarch64_a76_initfn(Object *obj)
> cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
> - cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
> - cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
> + SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
> + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
> cpu->id_afr0 = 0x00000000;
> cpu->isar.id_dfr0 = 0x04010088;
> cpu->isar.id_isar0 = 0x02101110;
> @@ -427,8 +424,8 @@ static void aarch64_a64fx_initfn(Object *obj)
> cpu->revidr = 0x00000000;
> cpu->ctr = 0x86668006;
> cpu->reset_sctlr = 0x30000180;
> - cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
> - cpu->isar.id_aa64pfr1 = 0x0000000000000000;
> + SET_IDREG(isar, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions */
> + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000);
> cpu->isar.id_aa64dfr0 = 0x0000000010305408;
> cpu->isar.id_aa64dfr1 = 0x0000000000000000;
> cpu->id_aa64afr0 = 0x0000000000000000;
> @@ -609,8 +606,8 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
> cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
> - cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
> - cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
> + SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
> + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
> cpu->id_afr0 = 0x00000000;
> cpu->isar.id_dfr0 = 0x04010088;
> cpu->isar.id_isar0 = 0x02101110;
> @@ -688,8 +685,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
> cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
> cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull;
> - cpu->isar.id_aa64pfr0 = 0x1101110120111112ull; /* GIC filled in later */
> - cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
> + SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in later */
> + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
> cpu->id_afr0 = 0x00000000;
> cpu->isar.id_dfr0 = 0x15011099;
> cpu->isar.id_isar0 = 0x02101110;
> @@ -925,8 +922,8 @@ static void aarch64_a710_initfn(Object *obj)
> cpu->isar.mvfr1 = 0x13211111;
> cpu->isar.mvfr2 = 0x00000043;
> cpu->isar.id_pfr2 = 0x00000011;
> - cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
> - cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
> + SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
> + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull);
> SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
> cpu->isar.id_aa64dfr0 = 0x000011f010305619ull;
> cpu->isar.id_aa64dfr1 = 0;
> @@ -1027,8 +1024,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
> cpu->isar.mvfr1 = 0x13211111;
> cpu->isar.mvfr2 = 0x00000043;
> cpu->isar.id_pfr2 = 0x00000011;
> - cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
> - cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
> + SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
> + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull);
> SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
> cpu->isar.id_aa64dfr0 = 0x000011f210305619ull;
> cpu->isar.id_aa64dfr1 = 0;
> @@ -1183,7 +1180,7 @@ void aarch64_max_tcg_initfn(Object *obj)
> t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */
> SET_IDREG(isar, ID_AA64ISAR2, t);
>
> - t = cpu->isar.id_aa64pfr0;
> + t = GET_IDREG(isar, ID_AA64PFR0);
> t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
> t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
> t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */
> @@ -1192,9 +1189,9 @@ void aarch64_max_tcg_initfn(Object *obj)
> t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
> t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */
> t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
> - cpu->isar.id_aa64pfr0 = t;
> + SET_IDREG(isar, ID_AA64PFR0, t);
>
> - t = cpu->isar.id_aa64pfr1;
> + t = GET_IDREG(isar, ID_AA64PFR1);
> t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
> t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
> /*
> @@ -1207,7 +1204,7 @@ void aarch64_max_tcg_initfn(Object *obj)
> t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
> t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */
> t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */
> - cpu->isar.id_aa64pfr1 = t;
> + SET_IDREG(isar, ID_AA64PFR1, t);
>
> t = cpu->isar.id_aa64mmfr0;
> t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH for-10.1 v5 04/13] arm/cpu: Store aa64pfr0/1 into the idregs array
2025-04-28 15:39 ` Eric Auger
@ 2025-04-29 9:38 ` Cornelia Huck
0 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-04-29 9:38 UTC (permalink / raw)
To: eric.auger, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini
On Mon, Apr 28 2025, Eric Auger <eric.auger@redhat.com> wrote:
> On 4/9/25 4:42 PM, Cornelia Huck wrote:
>> From: Eric Auger <eric.auger@redhat.com>
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Reviewed-by: Sebastian Ott <sebott@redhat.com>
>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
>> ---
>> target/arm/cpu-features.h | 40 ++++++++++++++++-----------------
>> target/arm/cpu.c | 29 ++++++++----------------
>> target/arm/cpu.h | 2 --
>> target/arm/cpu64.c | 14 ++++--------
>> target/arm/helper.c | 6 ++---
>> target/arm/hvf/hvf.c | 9 ++++----
>> target/arm/kvm.c | 24 +++++++++-----------
>> target/arm/tcg/cpu64.c | 47 ++++++++++++++++++---------------------
>> 8 files changed, 73 insertions(+), 98 deletions(-)
>> @@ -380,10 +378,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
>> * than skipping the reads and leaving 0, as we must avoid
>> * considering the values in every case.
>> */
>> - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0,
>> - ARM64_SYS_REG(3, 0, 0, 1, 0));
>> - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
>> - ARM64_SYS_REG(3, 0, 0, 1, 1));
>> + err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR0_EL1_IDX);
> Hum I think we have a conversion mistake here:
>
> +DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0)
> +DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1)
Indeed, wrong regs. Will fix.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH for-10.1 v5 05/13] arm/cpu: Store aa64mmfr0-3 into the idregs array
2025-04-09 14:42 [PATCH for-10.1 v5 00/13] arm: rework id register storage Cornelia Huck
` (3 preceding siblings ...)
2025-04-09 14:42 ` [PATCH for-10.1 v5 04/13] arm/cpu: Store aa64pfr0/1 " Cornelia Huck
@ 2025-04-09 14:42 ` Cornelia Huck
2025-04-09 14:42 ` [PATCH for-10.1 v5 06/13] arm/cpu: Store aa64dfr0/1 " Cornelia Huck
` (8 subsequent siblings)
13 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-04-09 14:42 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-features.h | 74 +++++++++++++++++++--------------------
target/arm/cpu.h | 4 ---
target/arm/cpu64.c | 8 ++---
target/arm/helper.c | 8 ++---
target/arm/hvf/hvf.c | 21 ++++++-----
target/arm/kvm.c | 12 +++----
target/arm/ptw.c | 6 ++--
target/arm/tcg/cpu64.c | 64 ++++++++++++++++-----------------
8 files changed, 95 insertions(+), 102 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 5cc4721e6406..36c35f6a434a 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -710,192 +710,192 @@ static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id)
static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
{
- return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
+ return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >= 1;
}
static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
{
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
+ unsigned t = FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN4_2);
return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
}
static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16) >= 2;
}
static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
{
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
+ unsigned t = FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16_2);
return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
}
static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
{
- return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
+ return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >= 0;
}
static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16) >= 1;
}
static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
{
- return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
+ return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN64) >= 0;
}
static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
{
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
+ unsigned t = FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN4_2);
return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
}
static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
{
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
+ unsigned t = FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN16_2);
return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
}
static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
{
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
+ unsigned t = FIELD_EX64_IDREG(id, ID_AA64MMFR0, TGRAN64_2);
return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
}
static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR0, FGT) != 0;
}
static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR0, ECV) > 0;
}
static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR0, ECV) > 1;
}
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR1, VH) != 0;
}
static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR1, LO) != 0;
}
static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) != 0;
}
static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) >= 2;
}
static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR1, PAN) >= 3;
}
static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HCX) != 0;
}
static inline bool isar_feature_aa64_afp(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, AFP) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR1, AFP) != 0;
}
static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, TIDCP1) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR1, TIDCP1) != 0;
}
static inline bool isar_feature_aa64_cmow(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, CMOW) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR1, CMOW) != 0;
}
static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HAFDBS) != 0;
}
static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR1, HAFDBS) >= 2;
}
static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR1, XNX) != 0;
}
static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR2, UAO) != 0;
}
static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR2, ST) != 0;
}
static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR2, AT) != 0;
}
static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR2, FWB) != 0;
}
static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR2, IDS) != 0;
}
static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR2, EVT) >= 1;
}
static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR2, EVT) >= 2;
}
static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR2, CCIDX) != 0;
}
static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR2, VARANGE) != 0;
}
static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR2, E0PD) != 0;
}
static inline bool isar_feature_aa64_nv(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) != 0;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) != 0;
}
static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) >= 2;
+ return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) >= 2;
}
static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 83ac125b97c5..30f27fb64aed 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1097,10 +1097,6 @@ struct ArchCPU {
uint32_t dbgdidr;
uint32_t dbgdevid;
uint32_t dbgdevid1;
- uint64_t id_aa64mmfr0;
- uint64_t id_aa64mmfr1;
- uint64_t id_aa64mmfr2;
- uint64_t id_aa64mmfr3;
uint64_t id_aa64dfr0;
uint64_t id_aa64dfr1;
uint64_t id_aa64smfr0;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 111b2514218e..6d51a53b0abb 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -623,12 +623,12 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
return;
}
- t = cpu->isar.id_aa64mmfr0;
+ t = GET_IDREG(&cpu->isar, ID_AA64MMFR0);
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */
- cpu->isar.id_aa64mmfr0 = t;
+ SET_IDREG(&cpu->isar, ID_AA64MMFR0, t);
}
static void aarch64_a57_initfn(Object *obj)
@@ -673,7 +673,7 @@ static void aarch64_a57_initfn(Object *obj)
SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
cpu->isar.id_aa64dfr0 = 0x10305106;
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
- cpu->isar.id_aa64mmfr0 = 0x00001124;
+ SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
cpu->isar.dbgdidr = 0x3516d000;
cpu->isar.dbgdevid = 0x01110f13;
cpu->isar.dbgdevid1 = 0x2;
@@ -735,7 +735,7 @@ static void aarch64_a53_initfn(Object *obj)
SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
cpu->isar.id_aa64dfr0 = 0x10305106;
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
- cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
+ SET_IDREG(isar, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */
cpu->isar.dbgdidr = 0x3516d000;
cpu->isar.dbgdevid = 0x00110f13;
cpu->isar.dbgdevid1 = 0x1;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 716d0570f6d6..15ca88b165e1 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8041,22 +8041,22 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64mmfr0 },
+ .resetvalue = GET_IDREG(isar, ID_AA64MMFR0)},
{ .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64mmfr1 },
+ .resetvalue = GET_IDREG(isar, ID_AA64MMFR1) },
{ .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64mmfr2 },
+ .resetvalue = GET_IDREG(isar, ID_AA64MMFR2) },
{ .name = "ID_AA64MMFR3_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64mmfr3 },
+ .resetvalue = GET_IDREG(isar, ID_AA64MMFR3) },
{ .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 9d37ca6bbbde..833681e9a28e 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -845,14 +845,17 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt)
return val;
}
-static void clamp_id_aa64mmfr0_parange_to_ipa_size(uint64_t *id_aa64mmfr0)
+static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARMISARegisters *isar)
{
uint32_t ipa_size = chosen_ipa_bit_size ?
chosen_ipa_bit_size : hvf_arm_get_max_ipa_bit_size();
+ uint64_t id_aa64mmfr0;
/* Clamp down the PARange to the IPA size the kernel supports. */
uint8_t index = round_down_to_parange_index(ipa_size);
- *id_aa64mmfr0 = (*id_aa64mmfr0 & ~R_ID_AA64MMFR0_PARANGE_MASK) | index;
+ id_aa64mmfr0 = GET_IDREG(isar, ID_AA64MMFR0);
+ id_aa64mmfr0 = (id_aa64mmfr0 & ~R_ID_AA64MMFR0_PARANGE_MASK) | index;
+ SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0);
}
static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
@@ -869,9 +872,9 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
{ HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] },
{ HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_IDX] },
/* Add ID_AA64ISAR2_EL1 here when HVF supports it */
- { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
- { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
- { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 },
+ { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.idregs[ID_AA64MMFR0_EL1_IDX] },
+ { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.idregs[ID_AA64MMFR1_EL1_IDX] },
+ { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.idregs[ID_AA64MMFR2_EL1_IDX] },
/* Add ID_AA64MMFR3_EL1 here when HVF supports it */
};
hv_vcpu_t fd;
@@ -898,7 +901,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr);
r |= hv_vcpu_destroy(fd);
- clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar.id_aa64mmfr0);
+ clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar);
/*
* Disable SME, which is not properly handled by QEMU hvf yet.
@@ -1066,12 +1069,12 @@ int hvf_arch_init_vcpu(CPUState *cpu)
/* We're limited to underlying hardware caps, override internal versions */
ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1,
- &arm_cpu->isar.id_aa64mmfr0);
+ &arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]);
assert_hvf_ok(ret);
- clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar.id_aa64mmfr0);
+ clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar);
ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1,
- arm_cpu->isar.id_aa64mmfr0);
+ arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]);
assert_hvf_ok(ret);
return 0;
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 44a5e219b051..5f3c42b94690 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -362,14 +362,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR1_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR2_EL1_IDX);
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0,
- ARM64_SYS_REG(3, 0, 0, 7, 0));
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,
- ARM64_SYS_REG(3, 0, 0, 7, 1));
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
- ARM64_SYS_REG(3, 0, 0, 7, 2));
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3,
- ARM64_SYS_REG(3, 0, 0, 7, 3));
+ err |= get_host_cpu_reg(fd, ahcf, ID_AA64MMFR0_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_AA64MMFR1_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_AA64MMFR2_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_AA64MMFR3_EL1_IDX);
/*
* Note that if AArch32 support is not present in the host,
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 43309003486b..79c7dabdc687 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -120,7 +120,7 @@ unsigned int arm_pamax(ARMCPU *cpu)
{
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
unsigned int parange =
- FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
+ FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANGE);
/*
* id_aa64mmfr0 is a read-only register so values outside of the
@@ -330,7 +330,7 @@ static bool granule_protection_check(CPUARMState *env, uint64_t paddress,
* physical address size is invalid.
*/
pps = FIELD_EX64(gpccr, GPCCR, PPS);
- if (pps > FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE)) {
+ if (pps > FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANGE)) {
goto fault_walk;
}
pps = pamax_map[pps];
@@ -1701,7 +1701,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
* ID_AA64MMFR0 is a read-only register so values outside of the
* supported mappings can be considered an implementation error.
*/
- ps = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
+ ps = FIELD_EX64_IDREG(&cpu->isar, ID_AA64MMFR0, PARANGE);
ps = MIN(ps, param.ps);
assert(ps < ARRAY_SIZE(pamax_map));
outputsize = pamax_map[ps];
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 478ef839bafa..439c29e69546 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -69,8 +69,8 @@ static void aarch64_a35_initfn(Object *obj)
cpu->isar.id_aa64dfr1 = 0;
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
SET_IDREG(isar, ID_AA64ISAR1, 0);
- cpu->isar.id_aa64mmfr0 = 0x00101122;
- cpu->isar.id_aa64mmfr1 = 0;
+ SET_IDREG(isar, ID_AA64MMFR0, 0x00101122);
+ SET_IDREG(isar, ID_AA64MMFR1, 0);
cpu->clidr = 0x0a200023;
cpu->dcz_blocksize = 4;
@@ -222,9 +222,9 @@ static void aarch64_a55_initfn(Object *obj)
cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
- cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+ SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull);
+ SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull);
+ SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull);
SET_IDREG(isar, ID_AA64PFR0, 0x0000000010112222ull);
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
@@ -312,7 +312,7 @@ static void aarch64_a72_initfn(Object *obj)
SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
cpu->isar.id_aa64dfr0 = 0x10305106;
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
- cpu->isar.id_aa64mmfr0 = 0x00001124;
+ SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
cpu->isar.dbgdidr = 0x3516d000;
cpu->isar.dbgdevid = 0x01110f13;
cpu->isar.dbgdevid1 = 0x2;
@@ -355,9 +355,9 @@ static void aarch64_a76_initfn(Object *obj)
cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
- cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+ SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull);
+ SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull);
+ SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull);
SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
@@ -430,9 +430,9 @@ static void aarch64_a64fx_initfn(Object *obj)
cpu->isar.id_aa64dfr1 = 0x0000000000000000;
cpu->id_aa64afr0 = 0x0000000000000000;
cpu->id_aa64afr1 = 0x0000000000000000;
- cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
- cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
+ SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122);
+ SET_IDREG(isar, ID_AA64MMFR1, 0x0000000011212100);
+ SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011);
SET_IDREG(isar, ID_AA64ISAR0, 0x0000000010211120);
SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000010001);
SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000);
@@ -603,9 +603,9 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
- cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+ SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull);
+ SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull);
+ SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull);
SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
@@ -682,9 +682,9 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->isar.id_aa64dfr1 = 0x00000000;
SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */
SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull);
- cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull;
+ SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull);
+ SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull),
+ SET_IDREG(isar, ID_AA64MMFR2, 0x0220011102101011ull),
SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in later */
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
@@ -931,9 +931,9 @@ static void aarch64_a710_initfn(Object *obj)
cpu->id_aa64afr1 = 0;
SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */
SET_IDREG(isar, ID_AA64ISAR1, 0x0010111101211052ull);
- cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull;
+ SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101122ull);
+ SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull);
+ SET_IDREG(isar, ID_AA64MMFR2, 0x1221011110101011ull);
cpu->clidr = 0x0000001482000023ull;
cpu->gm_blocksize = 4;
cpu->ctr = 0x000000049444c004ull;
@@ -1033,9 +1033,9 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->id_aa64afr1 = 0;
SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto and FEAT_RNG */
SET_IDREG(isar, ID_AA64ISAR1, 0x0011111101211052ull);
- cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x1221011112101011ull;
+ SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101125ull);
+ SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull);
+ SET_IDREG(isar, ID_AA64MMFR2, 0x1221011112101011ull);
cpu->clidr = 0x0000001482000023ull;
cpu->gm_blocksize = 4;
cpu->ctr = 0x00000004b444c004ull;
@@ -1206,7 +1206,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */
SET_IDREG(isar, ID_AA64PFR1, t);
- t = cpu->isar.id_aa64mmfr0;
+ t = GET_IDREG(isar, ID_AA64MMFR0);
t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
@@ -1214,9 +1214,9 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */
- cpu->isar.id_aa64mmfr0 = t;
+ SET_IDREG(isar, ID_AA64MMFR0, t);
- t = cpu->isar.id_aa64mmfr1;
+ t = GET_IDREG(isar, ID_AA64MMFR1);
t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */
t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
@@ -1229,9 +1229,9 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR1, AFP, 1); /* FEAT_AFP */
t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */
t = FIELD_DP64(t, ID_AA64MMFR1, CMOW, 1); /* FEAT_CMOW */
- cpu->isar.id_aa64mmfr1 = t;
+ SET_IDREG(isar, ID_AA64MMFR1, t);
- t = cpu->isar.id_aa64mmfr2;
+ t = GET_IDREG(isar, ID_AA64MMFR2);
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
@@ -1245,11 +1245,9 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */
t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
- cpu->isar.id_aa64mmfr2 = t;
+ SET_IDREG(isar, ID_AA64MMFR2, t);
- t = cpu->isar.id_aa64mmfr3;
- t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */
- cpu->isar.id_aa64mmfr3 = t;
+ FIELD_DP64_IDREG(isar, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */
t = GET_IDREG(isar, ID_AA64ZFR0);
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH for-10.1 v5 06/13] arm/cpu: Store aa64dfr0/1 into the idregs array
2025-04-09 14:42 [PATCH for-10.1 v5 00/13] arm: rework id register storage Cornelia Huck
` (4 preceding siblings ...)
2025-04-09 14:42 ` [PATCH for-10.1 v5 05/13] arm/cpu: Store aa64mmfr0-3 " Cornelia Huck
@ 2025-04-09 14:42 ` Cornelia Huck
2025-04-28 15:56 ` Eric Auger
2025-04-09 14:42 ` [PATCH for-10.1 v5 07/13] arm/cpu: Store aa64smfr0 " Cornelia Huck
` (7 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Cornelia Huck @ 2025-04-09 14:42 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-features.h | 16 ++++++++--------
target/arm/cpu.c | 15 +++++----------
target/arm/cpu.h | 2 --
target/arm/cpu64.c | 4 ++--
target/arm/helper.c | 4 ++--
target/arm/hvf/hvf.c | 4 ++--
target/arm/internals.h | 6 +++---
target/arm/kvm.c | 12 +++++-------
target/arm/tcg/cpu64.c | 33 +++++++++++++++++----------------
9 files changed, 44 insertions(+), 52 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 36c35f6a434a..7f6331ca437d 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -900,30 +900,30 @@ static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id)
static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
- FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
+ return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >= 4 &&
+ FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) != 0xf;
}
static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
- FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
+ return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >= 5 &&
+ FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) != 0xf;
}
static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 &&
- FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
+ return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >= 6 &&
+ FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) != 0xf;
}
static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
+ return FIELD_EX64_IDREG(id, ID_AA64DFR0, DEBUGVER) >= 8;
}
static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
{
- return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
+ return FIELD_SEX64_IDREG(id, ID_AA64DFR0, DOUBLELOCK) >= 0;
}
static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 23be9ab97334..7bd20d1f2710 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2353,8 +2353,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
cpu);
#endif
} else {
- cpu->isar.id_aa64dfr0 =
- FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
+ FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMUVER, 0);
cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
cpu->pmceid0 = 0;
cpu->pmceid1 = 0;
@@ -2414,19 +2413,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* try to access the non-existent system registers for them.
*/
/* FEAT_SPE (Statistical Profiling Extension) */
- cpu->isar.id_aa64dfr0 =
- FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
+ FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMSVER, 0);
/* FEAT_TRBE (Trace Buffer Extension) */
- cpu->isar.id_aa64dfr0 =
- FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
+ FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEBUFFER, 0);
/* FEAT_TRF (Self-hosted Trace Extension) */
- cpu->isar.id_aa64dfr0 =
- FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
+ FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEFILT, 0);
cpu->isar.id_dfr0 =
FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0);
/* Trace Macrocell system register access */
- cpu->isar.id_aa64dfr0 =
- FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0);
+ FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEVER, 0);
cpu->isar.id_dfr0 =
FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0);
/* Memory mapped trace */
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 30f27fb64aed..37bb337b3c71 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1097,8 +1097,6 @@ struct ArchCPU {
uint32_t dbgdidr;
uint32_t dbgdevid;
uint32_t dbgdevid1;
- uint64_t id_aa64dfr0;
- uint64_t id_aa64dfr1;
uint64_t id_aa64smfr0;
uint64_t reset_pmcr_el0;
uint64_t idregs[NUM_ID_IDX];
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 6d51a53b0abb..4ba53f75ed96 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -671,7 +671,7 @@ static void aarch64_a57_initfn(Object *obj)
cpu->isar.id_isar5 = 0x00011121;
cpu->isar.id_isar6 = 0;
SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
- cpu->isar.id_aa64dfr0 = 0x10305106;
+ SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
cpu->isar.dbgdidr = 0x3516d000;
@@ -733,7 +733,7 @@ static void aarch64_a53_initfn(Object *obj)
cpu->isar.id_isar5 = 0x00011121;
cpu->isar.id_isar6 = 0;
SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
- cpu->isar.id_aa64dfr0 = 0x10305106;
+ SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
SET_IDREG(isar, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */
cpu->isar.dbgdidr = 0x3516d000;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 15ca88b165e1..8efe508306e5 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7961,12 +7961,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64dfr0 },
+ .resetvalue = GET_IDREG(isar, ID_AA64DFR0) },
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64dfr1 },
+ .resetvalue = GET_IDREG(isar, ID_AA64DFR1) },
{ .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 833681e9a28e..b0c45d4ca294 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -867,8 +867,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
} regs[] = {
{ HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_IDX] },
{ HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_IDX] },
- { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 },
- { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },
+ { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_IDX] },
+ { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_IDX] },
{ HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] },
{ HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_IDX] },
/* Add ID_AA64ISAR2_EL1 here when HVF supports it */
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 28585c07555b..cafc8e66324f 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1170,7 +1170,7 @@ static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
static inline int arm_num_brps(ARMCPU *cpu)
{
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1;
+ return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, BRPS) + 1;
} else {
return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1;
}
@@ -1184,7 +1184,7 @@ static inline int arm_num_brps(ARMCPU *cpu)
static inline int arm_num_wrps(ARMCPU *cpu)
{
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1;
+ return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, WRPS) + 1;
} else {
return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1;
}
@@ -1198,7 +1198,7 @@ static inline int arm_num_wrps(ARMCPU *cpu)
static inline int arm_num_ctx_cmps(ARMCPU *cpu)
{
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1;
+ return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, CTX_CMPS) + 1;
} else {
return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1;
}
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 5f3c42b94690..e999d98dcf7f 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -355,10 +355,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX);
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0,
ARM64_SYS_REG(3, 0, 0, 4, 5));
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0,
- ARM64_SYS_REG(3, 0, 0, 5, 0));
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1,
- ARM64_SYS_REG(3, 0, 0, 5, 1));
+ err |= get_host_cpu_reg(fd, ahcf, ID_AA64DFR0_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_AA64DFR1_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR1_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR2_EL1_IDX);
@@ -427,10 +425,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* We only do this if the CPU supports AArch32 at EL1.
*/
if (FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL1) >= 2) {
- int wrps = FIELD_EX64(&ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS);
- int brps = FIELD_EX64(&ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS);
+ int wrps = FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, WRPS);
+ int brps = FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, BRPS);
int ctx_cmps =
- FIELD_EX64(&ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS);
+ FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, CTX_CMPS);
int version = 6; /* ARMv8 debug architecture */
bool has_el3 =
!!FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL3);
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 439c29e69546..41077b3dcd08 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -65,8 +65,8 @@ static void aarch64_a35_initfn(Object *obj)
cpu->isar.id_isar5 = 0x00011121;
SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
SET_IDREG(isar, ID_AA64PFR1, 0);
- cpu->isar.id_aa64dfr0 = 0x10305106;
- cpu->isar.id_aa64dfr1 = 0;
+ SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
+ SET_IDREG(isar, ID_AA64DFR1, 0);
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
SET_IDREG(isar, ID_AA64ISAR1, 0);
SET_IDREG(isar, ID_AA64MMFR0, 0x00101122);
@@ -219,7 +219,7 @@ static void aarch64_a55_initfn(Object *obj)
cpu->clidr = 0x82000023;
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
cpu->dcz_blocksize = 4; /* 64 bytes */
- cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
+ SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull);
SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull);
@@ -310,7 +310,7 @@ static void aarch64_a72_initfn(Object *obj)
cpu->isar.id_isar4 = 0x00011142;
cpu->isar.id_isar5 = 0x00011121;
SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
- cpu->isar.id_aa64dfr0 = 0x10305106;
+ SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
cpu->isar.dbgdidr = 0x3516d000;
@@ -352,7 +352,7 @@ static void aarch64_a76_initfn(Object *obj)
cpu->clidr = 0x82000023;
cpu->ctr = 0x8444C004;
cpu->dcz_blocksize = 4;
- cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
+ SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull),
SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull);
@@ -426,8 +426,8 @@ static void aarch64_a64fx_initfn(Object *obj)
cpu->reset_sctlr = 0x30000180;
SET_IDREG(isar, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions */
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000);
- cpu->isar.id_aa64dfr0 = 0x0000000010305408;
- cpu->isar.id_aa64dfr1 = 0x0000000000000000;
+ SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408),
+ SET_IDREG(isar, ID_AA64DFR1, 0x0000000000000000),
cpu->id_aa64afr0 = 0x0000000000000000;
cpu->id_aa64afr1 = 0x0000000000000000;
SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122);
@@ -600,7 +600,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
cpu->clidr = 0x82000023;
cpu->ctr = 0x8444c004;
cpu->dcz_blocksize = 4;
- cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
+ SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull);
SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull);
@@ -678,8 +678,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->dcz_blocksize = 4;
cpu->id_aa64afr0 = 0x00000000;
cpu->id_aa64afr1 = 0x00000000;
- cpu->isar.id_aa64dfr0 = 0x000001f210305519ull;
- cpu->isar.id_aa64dfr1 = 0x00000000;
+ SET_IDREG(isar, ID_AA64DFR0, 0x000001f210305519ull),
+ SET_IDREG(isar, ID_AA64DFR1, 0x00000000),
SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */
SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull);
SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull);
@@ -925,8 +925,9 @@ static void aarch64_a710_initfn(Object *obj)
SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull);
SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
- cpu->isar.id_aa64dfr0 = 0x000011f010305619ull;
- cpu->isar.id_aa64dfr1 = 0;
+ SET_IDREG(isar, ID_AA64DFR0, 0x000011f010305619ull);
+ SET_IDREG(isar, ID_AA64DFR0, 0x000011f010305619ull);
+ SET_IDREG(isar, ID_AA64DFR1, 0);
cpu->id_aa64afr0 = 0;
cpu->id_aa64afr1 = 0;
SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */
@@ -1027,8 +1028,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull);
SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
- cpu->isar.id_aa64dfr0 = 0x000011f210305619ull;
- cpu->isar.id_aa64dfr1 = 0;
+ SET_IDREG(isar, ID_AA64DFR0, 0x000011f210305619ull);
+ SET_IDREG(isar, ID_AA64DFR1, 0);
cpu->id_aa64afr0 = 0;
cpu->id_aa64afr1 = 0;
SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto and FEAT_RNG */
@@ -1261,11 +1262,11 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
SET_IDREG(isar, ID_AA64ZFR0, t);
- t = cpu->isar.id_aa64dfr0;
+ t = GET_IDREG(isar, ID_AA64DFR0);
t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */
- cpu->isar.id_aa64dfr0 = t;
+ SET_IDREG(isar, ID_AA64DFR0, t);
t = cpu->isar.id_aa64smfr0;
t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH for-10.1 v5 06/13] arm/cpu: Store aa64dfr0/1 into the idregs array
2025-04-09 14:42 ` [PATCH for-10.1 v5 06/13] arm/cpu: Store aa64dfr0/1 " Cornelia Huck
@ 2025-04-28 15:56 ` Eric Auger
2025-04-29 9:48 ` Cornelia Huck
0 siblings, 1 reply; 29+ messages in thread
From: Eric Auger @ 2025-04-28 15:56 UTC (permalink / raw)
To: Cornelia Huck, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini
On 4/9/25 4:42 PM, Cornelia Huck wrote:
> From: Eric Auger <eric.auger@redhat.com>
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Sebastian Ott <sebott@redhat.com>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
> ---
> target/arm/cpu-features.h | 16 ++++++++--------
> target/arm/cpu.c | 15 +++++----------
> target/arm/cpu.h | 2 --
> target/arm/cpu64.c | 4 ++--
> target/arm/helper.c | 4 ++--
> target/arm/hvf/hvf.c | 4 ++--
> target/arm/internals.h | 6 +++---
> target/arm/kvm.c | 12 +++++-------
> target/arm/tcg/cpu64.c | 33 +++++++++++++++++----------------
> 9 files changed, 44 insertions(+), 52 deletions(-)
>
> diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
> index 36c35f6a434a..7f6331ca437d 100644
> --- a/target/arm/cpu-features.h
> +++ b/target/arm/cpu-features.h
> @@ -900,30 +900,30 @@ static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id)
>
> static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
> - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
> + return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >= 4 &&
> + FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) != 0xf;
> }
>
> static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
> - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
> + return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >= 5 &&
> + FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) != 0xf;
> }
>
> static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 &&
> - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
> + return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >= 6 &&
> + FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) != 0xf;
> }
>
> static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
> + return FIELD_EX64_IDREG(id, ID_AA64DFR0, DEBUGVER) >= 8;
> }
>
> static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
> {
> - return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
> + return FIELD_SEX64_IDREG(id, ID_AA64DFR0, DOUBLELOCK) >= 0;
> }
>
> static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 23be9ab97334..7bd20d1f2710 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2353,8 +2353,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> cpu);
> #endif
> } else {
> - cpu->isar.id_aa64dfr0 =
> - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
> + FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMUVER, 0);
> cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
> cpu->pmceid0 = 0;
> cpu->pmceid1 = 0;
> @@ -2414,19 +2413,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
> * try to access the non-existent system registers for them.
> */
> /* FEAT_SPE (Statistical Profiling Extension) */
> - cpu->isar.id_aa64dfr0 =
> - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
> + FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMSVER, 0);
> /* FEAT_TRBE (Trace Buffer Extension) */
> - cpu->isar.id_aa64dfr0 =
> - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
> + FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEBUFFER, 0);
> /* FEAT_TRF (Self-hosted Trace Extension) */
> - cpu->isar.id_aa64dfr0 =
> - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
> + FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEFILT, 0);
> cpu->isar.id_dfr0 =
> FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0);
> /* Trace Macrocell system register access */
> - cpu->isar.id_aa64dfr0 =
> - FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0);
> + FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEVER, 0);
> cpu->isar.id_dfr0 =
> FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0);
> /* Memory mapped trace */
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 30f27fb64aed..37bb337b3c71 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1097,8 +1097,6 @@ struct ArchCPU {
> uint32_t dbgdidr;
> uint32_t dbgdevid;
> uint32_t dbgdevid1;
> - uint64_t id_aa64dfr0;
> - uint64_t id_aa64dfr1;
> uint64_t id_aa64smfr0;
> uint64_t reset_pmcr_el0;
> uint64_t idregs[NUM_ID_IDX];
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 6d51a53b0abb..4ba53f75ed96 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -671,7 +671,7 @@ static void aarch64_a57_initfn(Object *obj)
> cpu->isar.id_isar5 = 0x00011121;
> cpu->isar.id_isar6 = 0;
> SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> - cpu->isar.id_aa64dfr0 = 0x10305106;
> + SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
> SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
> cpu->isar.dbgdidr = 0x3516d000;
> @@ -733,7 +733,7 @@ static void aarch64_a53_initfn(Object *obj)
> cpu->isar.id_isar5 = 0x00011121;
> cpu->isar.id_isar6 = 0;
> SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> - cpu->isar.id_aa64dfr0 = 0x10305106;
> + SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
> SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> SET_IDREG(isar, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */
> cpu->isar.dbgdidr = 0x3516d000;
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 15ca88b165e1..8efe508306e5 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -7961,12 +7961,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa64_tid3,
> - .resetvalue = cpu->isar.id_aa64dfr0 },
> + .resetvalue = GET_IDREG(isar, ID_AA64DFR0) },
> { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa64_tid3,
> - .resetvalue = cpu->isar.id_aa64dfr1 },
> + .resetvalue = GET_IDREG(isar, ID_AA64DFR1) },
> { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
> .access = PL1_R, .type = ARM_CP_CONST,
> diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
> index 833681e9a28e..b0c45d4ca294 100644
> --- a/target/arm/hvf/hvf.c
> +++ b/target/arm/hvf/hvf.c
> @@ -867,8 +867,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> } regs[] = {
> { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.idregs[ID_AA64PFR0_EL1_IDX] },
> { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.idregs[ID_AA64PFR1_EL1_IDX] },
> - { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 },
> - { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },
> + { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.idregs[ID_AA64DFR0_EL1_IDX] },
> + { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.idregs[ID_AA64DFR1_EL1_IDX] },
> { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.idregs[ID_AA64ISAR0_EL1_IDX] },
> { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.idregs[ID_AA64ISAR1_EL1_IDX] },
> /* Add ID_AA64ISAR2_EL1 here when HVF supports it */
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index 28585c07555b..cafc8e66324f 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -1170,7 +1170,7 @@ static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
> static inline int arm_num_brps(ARMCPU *cpu)
> {
> if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
> - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1;
> + return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, BRPS) + 1;
> } else {
> return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1;
> }
> @@ -1184,7 +1184,7 @@ static inline int arm_num_brps(ARMCPU *cpu)
> static inline int arm_num_wrps(ARMCPU *cpu)
> {
> if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
> - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1;
> + return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, WRPS) + 1;
> } else {
> return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1;
> }
> @@ -1198,7 +1198,7 @@ static inline int arm_num_wrps(ARMCPU *cpu)
> static inline int arm_num_ctx_cmps(ARMCPU *cpu)
> {
> if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
> - return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1;
> + return FIELD_EX64_IDREG(&cpu->isar, ID_AA64DFR0, CTX_CMPS) + 1;
> } else {
> return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1;
> }
> diff --git a/target/arm/kvm.c b/target/arm/kvm.c
> index 5f3c42b94690..e999d98dcf7f 100644
> --- a/target/arm/kvm.c
> +++ b/target/arm/kvm.c
> @@ -355,10 +355,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX);
> err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0,
> ARM64_SYS_REG(3, 0, 0, 4, 5));
> - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0,
> - ARM64_SYS_REG(3, 0, 0, 5, 0));
> - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1,
> - ARM64_SYS_REG(3, 0, 0, 5, 1));
> + err |= get_host_cpu_reg(fd, ahcf, ID_AA64DFR0_EL1_IDX);
> + err |= get_host_cpu_reg(fd, ahcf, ID_AA64DFR1_EL1_IDX);
> err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX);
> err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR1_EL1_IDX);
> err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR2_EL1_IDX);
> @@ -427,10 +425,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> * We only do this if the CPU supports AArch32 at EL1.
> */
> if (FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL1) >= 2) {
> - int wrps = FIELD_EX64(&ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS);
> - int brps = FIELD_EX64(&ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS);
> + int wrps = FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, WRPS);
> + int brps = FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, BRPS);
> int ctx_cmps =
> - FIELD_EX64(&ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS);
> + FIELD_EX64_IDREG(&ahcf->isar, ID_AA64DFR0, CTX_CMPS);
> int version = 6; /* ARMv8 debug architecture */
> bool has_el3 =
> !!FIELD_EX32_IDREG(&ahcf->isar, ID_AA64PFR0, EL3);
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index 439c29e69546..41077b3dcd08 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -65,8 +65,8 @@ static void aarch64_a35_initfn(Object *obj)
> cpu->isar.id_isar5 = 0x00011121;
> SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> SET_IDREG(isar, ID_AA64PFR1, 0);
> - cpu->isar.id_aa64dfr0 = 0x10305106;
> - cpu->isar.id_aa64dfr1 = 0;
> + SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
> + SET_IDREG(isar, ID_AA64DFR1, 0);
> SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> SET_IDREG(isar, ID_AA64ISAR1, 0);
> SET_IDREG(isar, ID_AA64MMFR0, 0x00101122);
> @@ -219,7 +219,7 @@ static void aarch64_a55_initfn(Object *obj)
> cpu->clidr = 0x82000023;
> cpu->ctr = 0x84448004; /* L1Ip = VIPT */
> cpu->dcz_blocksize = 4; /* 64 bytes */
> - cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
> + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull);
> SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
> SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
> SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull);
> @@ -310,7 +310,7 @@ static void aarch64_a72_initfn(Object *obj)
> cpu->isar.id_isar4 = 0x00011142;
> cpu->isar.id_isar5 = 0x00011121;
> SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> - cpu->isar.id_aa64dfr0 = 0x10305106;
> + SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
> SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> SET_IDREG(isar, ID_AA64MMFR0, 0x00001124);
> cpu->isar.dbgdidr = 0x3516d000;
> @@ -352,7 +352,7 @@ static void aarch64_a76_initfn(Object *obj)
> cpu->clidr = 0x82000023;
> cpu->ctr = 0x8444C004;
> cpu->dcz_blocksize = 4;
> - cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
> + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull),
> SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
> SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
> SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull);
> @@ -426,8 +426,8 @@ static void aarch64_a64fx_initfn(Object *obj)
> cpu->reset_sctlr = 0x30000180;
> SET_IDREG(isar, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions */
> SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000);
> - cpu->isar.id_aa64dfr0 = 0x0000000010305408;
> - cpu->isar.id_aa64dfr1 = 0x0000000000000000;
> + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408),
> + SET_IDREG(isar, ID_AA64DFR1, 0x0000000000000000),
> cpu->id_aa64afr0 = 0x0000000000000000;
> cpu->id_aa64afr1 = 0x0000000000000000;
> SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122);
> @@ -600,7 +600,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
> cpu->clidr = 0x82000023;
> cpu->ctr = 0x8444c004;
> cpu->dcz_blocksize = 4;
> - cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
> + SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull);
> SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull);
> SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull);
> SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull);
> @@ -678,8 +678,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
> cpu->dcz_blocksize = 4;
> cpu->id_aa64afr0 = 0x00000000;
> cpu->id_aa64afr1 = 0x00000000;
> - cpu->isar.id_aa64dfr0 = 0x000001f210305519ull;
> - cpu->isar.id_aa64dfr1 = 0x00000000;
> + SET_IDREG(isar, ID_AA64DFR0, 0x000001f210305519ull),
> + SET_IDREG(isar, ID_AA64DFR1, 0x00000000),
> SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */
> SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull);
> SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull);
> @@ -925,8 +925,9 @@ static void aarch64_a710_initfn(Object *obj)
> SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
> SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull);
> SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
> - cpu->isar.id_aa64dfr0 = 0x000011f010305619ull;
> - cpu->isar.id_aa64dfr1 = 0;
> + SET_IDREG(isar, ID_AA64DFR0, 0x000011f010305619ull);
> + SET_IDREG(isar, ID_AA64DFR0, 0x000011f010305619ull);
this line is doubled.
Eric
> + SET_IDREG(isar, ID_AA64DFR1, 0);
> cpu->id_aa64afr0 = 0;
> cpu->id_aa64afr1 = 0;
> SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */
> @@ -1027,8 +1028,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
> SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
> SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull);
> SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
> - cpu->isar.id_aa64dfr0 = 0x000011f210305619ull;
> - cpu->isar.id_aa64dfr1 = 0;
> + SET_IDREG(isar, ID_AA64DFR0, 0x000011f210305619ull);
> + SET_IDREG(isar, ID_AA64DFR1, 0);
> cpu->id_aa64afr0 = 0;
> cpu->id_aa64afr1 = 0;
> SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto and FEAT_RNG */
> @@ -1261,11 +1262,11 @@ void aarch64_max_tcg_initfn(Object *obj)
> t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
> SET_IDREG(isar, ID_AA64ZFR0, t);
>
> - t = cpu->isar.id_aa64dfr0;
> + t = GET_IDREG(isar, ID_AA64DFR0);
> t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */
> t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
> t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */
> - cpu->isar.id_aa64dfr0 = t;
> + SET_IDREG(isar, ID_AA64DFR0, t);
>
> t = cpu->isar.id_aa64smfr0;
> t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH for-10.1 v5 06/13] arm/cpu: Store aa64dfr0/1 into the idregs array
2025-04-28 15:56 ` Eric Auger
@ 2025-04-29 9:48 ` Cornelia Huck
0 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-04-29 9:48 UTC (permalink / raw)
To: eric.auger, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini
On Mon, Apr 28 2025, Eric Auger <eric.auger@redhat.com> wrote:
> On 4/9/25 4:42 PM, Cornelia Huck wrote:
>> From: Eric Auger <eric.auger@redhat.com>
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Reviewed-by: Sebastian Ott <sebott@redhat.com>
>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
>> ---
>> target/arm/cpu-features.h | 16 ++++++++--------
>> target/arm/cpu.c | 15 +++++----------
>> target/arm/cpu.h | 2 --
>> target/arm/cpu64.c | 4 ++--
>> target/arm/helper.c | 4 ++--
>> target/arm/hvf/hvf.c | 4 ++--
>> target/arm/internals.h | 6 +++---
>> target/arm/kvm.c | 12 +++++-------
>> target/arm/tcg/cpu64.c | 33 +++++++++++++++++----------------
>> 9 files changed, 44 insertions(+), 52 deletions(-)
>> @@ -925,8 +925,9 @@ static void aarch64_a710_initfn(Object *obj)
>> SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
>> SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull);
>> SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
>> - cpu->isar.id_aa64dfr0 = 0x000011f010305619ull;
>> - cpu->isar.id_aa64dfr1 = 0;
>> + SET_IDREG(isar, ID_AA64DFR0, 0x000011f010305619ull);
>> + SET_IDREG(isar, ID_AA64DFR0, 0x000011f010305619ull);
> this line is doubled.
Indeed, fixing.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH for-10.1 v5 07/13] arm/cpu: Store aa64smfr0 into the idregs array
2025-04-09 14:42 [PATCH for-10.1 v5 00/13] arm: rework id register storage Cornelia Huck
` (5 preceding siblings ...)
2025-04-09 14:42 ` [PATCH for-10.1 v5 06/13] arm/cpu: Store aa64dfr0/1 " Cornelia Huck
@ 2025-04-09 14:42 ` Cornelia Huck
2025-04-09 14:42 ` [PATCH for-10.1 v5 08/13] arm/cpu: Store id_isar0-7 " Cornelia Huck
` (6 subsequent siblings)
13 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-04-09 14:42 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-features.h | 6 +++---
target/arm/cpu.h | 1 -
target/arm/cpu64.c | 7 ++-----
target/arm/helper.c | 2 +-
target/arm/kvm.c | 3 +--
target/arm/tcg/cpu64.c | 4 ++--
6 files changed, 9 insertions(+), 14 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 7f6331ca437d..1ac1f3e95984 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -978,17 +978,17 @@ static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64);
+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, F64F64);
}
static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf;
+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, I16I64) == 0xf;
}
static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64);
+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, FA64);
}
/*
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 37bb337b3c71..a3a3b8031eed 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1097,7 +1097,6 @@ struct ArchCPU {
uint32_t dbgdidr;
uint32_t dbgdevid;
uint32_t dbgdevid1;
- uint64_t id_aa64smfr0;
uint64_t reset_pmcr_el0;
uint64_t idregs[NUM_ID_IDX];
} isar;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 4ba53f75ed96..c8ab8761282a 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -328,7 +328,7 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
if (vq_map == 0) {
if (!cpu_isar_feature(aa64_sme, cpu)) {
- cpu->isar.id_aa64smfr0 = 0;
+ SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0);
return;
}
@@ -381,11 +381,8 @@ static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp)
static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
- uint64_t t;
- t = cpu->isar.id_aa64smfr0;
- t = FIELD_DP64(t, ID_AA64SMFR0, FA64, value);
- cpu->isar.id_aa64smfr0 = t;
+ FIELD_DP64_IDREG(&cpu->isar, ID_AA64SMFR0, FA64, value);
}
#ifdef CONFIG_USER_ONLY
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8efe508306e5..275e590876bf 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7946,7 +7946,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64smfr0 },
+ .resetvalue = GET_IDREG(isar, ID_AA64SMFR0)},
{ .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index e999d98dcf7f..a73ff0a603bc 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -353,8 +353,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err = 0;
} else {
err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX);
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0,
- ARM64_SYS_REG(3, 0, 0, 4, 5));
+ err |= get_host_cpu_reg(fd, ahcf, ID_AA64SMFR0_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_AA64DFR0_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_AA64DFR1_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_AA64ISAR0_EL1_IDX);
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 41077b3dcd08..cadc1258fc40 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1268,7 +1268,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */
SET_IDREG(isar, ID_AA64DFR0, t);
- t = cpu->isar.id_aa64smfr0;
+ t = GET_IDREG(isar, ID_AA64SMFR0);
t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */
t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */
t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */
@@ -1276,7 +1276,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */
t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */
t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */
- cpu->isar.id_aa64smfr0 = t;
+ SET_IDREG(isar, ID_AA64SMFR0, t);
/* Replicate the same data to the 32-bit id registers. */
aa32_max_features(cpu);
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH for-10.1 v5 08/13] arm/cpu: Store id_isar0-7 into the idregs array
2025-04-09 14:42 [PATCH for-10.1 v5 00/13] arm: rework id register storage Cornelia Huck
` (6 preceding siblings ...)
2025-04-09 14:42 ` [PATCH for-10.1 v5 07/13] arm/cpu: Store aa64smfr0 " Cornelia Huck
@ 2025-04-09 14:42 ` Cornelia Huck
2025-04-28 16:04 ` Eric Auger
2025-04-09 14:43 ` [PATCH for-10.1 v5 09/13] arm/cpu: Store id_pfr0/1/2 " Cornelia Huck
` (5 subsequent siblings)
13 siblings, 1 reply; 29+ messages in thread
From: Cornelia Huck @ 2025-04-09 14:42 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
hw/intc/armv7m_nvic.c | 12 ++--
target/arm/cpu-features.h | 36 +++++-----
target/arm/cpu.c | 24 +++----
target/arm/cpu.h | 7 --
target/arm/cpu64.c | 28 ++++----
target/arm/helper.c | 14 ++--
target/arm/kvm.c | 21 ++----
target/arm/tcg/cpu-v7m.c | 90 +++++++++++++-----------
target/arm/tcg/cpu32.c | 144 +++++++++++++++++++++-----------------
target/arm/tcg/cpu64.c | 108 ++++++++++++++--------------
10 files changed, 243 insertions(+), 241 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 7212c87c68ec..55e726be7a2c 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1303,32 +1303,32 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_isar0;
+ return GET_IDREG(&cpu->isar, ID_ISAR0);
case 0xd64: /* ISAR1. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_isar1;
+ return GET_IDREG(&cpu->isar, ID_ISAR1);
case 0xd68: /* ISAR2. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_isar2;
+ return GET_IDREG(&cpu->isar, ID_ISAR2);
case 0xd6c: /* ISAR3. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_isar3;
+ return GET_IDREG(&cpu->isar, ID_ISAR3);
case 0xd70: /* ISAR4. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_isar4;
+ return GET_IDREG(&cpu->isar, ID_ISAR4);
case 0xd74: /* ISAR5. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_isar5;
+ return GET_IDREG(&cpu->isar, ID_ISAR5);
case 0xd78: /* CLIDR */
return cpu->clidr;
case 0xd7c: /* CTR */
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 1ac1f3e95984..003cf735e8ef 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -45,93 +45,93 @@
*/
static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
+ return FIELD_EX32_IDREG(id, ID_ISAR0, DIVIDE) != 0;
}
static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
+ return FIELD_EX32_IDREG(id, ID_ISAR0, DIVIDE) > 1;
}
static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
{
/* (M-profile) low-overhead loops and branch future */
- return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
+ return FIELD_EX32_IDREG(id, ID_ISAR0, CMPBRANCH) >= 3;
}
static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
+ return FIELD_EX32_IDREG(id, ID_ISAR1, JAZELLE) != 0;
}
static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
+ return FIELD_EX32_IDREG(id, ID_ISAR5, AES) != 0;
}
static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
+ return FIELD_EX32_IDREG(id, ID_ISAR5, AES) > 1;
}
static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
+ return FIELD_EX32_IDREG(id, ID_ISAR5, SHA1) != 0;
}
static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
+ return FIELD_EX32_IDREG(id, ID_ISAR5, SHA2) != 0;
}
static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
+ return FIELD_EX32_IDREG(id, ID_ISAR5, CRC32) != 0;
}
static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
+ return FIELD_EX32_IDREG(id, ID_ISAR5, RDM) != 0;
}
static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
+ return FIELD_EX32_IDREG(id, ID_ISAR5, VCMA) != 0;
}
static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
+ return FIELD_EX32_IDREG(id, ID_ISAR6, JSCVT) != 0;
}
static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
+ return FIELD_EX32_IDREG(id, ID_ISAR6, DP) != 0;
}
static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
+ return FIELD_EX32_IDREG(id, ID_ISAR6, FHM) != 0;
}
static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
+ return FIELD_EX32_IDREG(id, ID_ISAR6, SB) != 0;
}
static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
+ return FIELD_EX32_IDREG(id, ID_ISAR6, SPECRES) != 0;
}
static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0;
+ return FIELD_EX32_IDREG(id, ID_ISAR6, BF16) != 0;
}
static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0;
+ return FIELD_EX32_IDREG(id, ID_ISAR6, I8MM) != 0;
}
static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7bd20d1f2710..45d922110c17 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2132,10 +2132,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
FIELD_DP64_IDREG(isar, ID_AA64PFR0, FP, 0xf);
- u = cpu->isar.id_isar6;
+ u = GET_IDREG(isar, ID_ISAR6);
u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
- cpu->isar.id_isar6 = u;
+ SET_IDREG(isar, ID_ISAR6, u);
u = cpu->isar.mvfr0;
u = FIELD_DP32(u, MVFR0, FPSP, 0);
@@ -2187,20 +2187,20 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
FIELD_DP64_IDREG(isar, ID_AA64PFR0, ADVSIMD, 0xf);
- u = cpu->isar.id_isar5;
+ u = GET_IDREG(isar, ID_ISAR5);
u = FIELD_DP32(u, ID_ISAR5, AES, 0);
u = FIELD_DP32(u, ID_ISAR5, SHA1, 0);
u = FIELD_DP32(u, ID_ISAR5, SHA2, 0);
u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
- cpu->isar.id_isar5 = u;
+ SET_IDREG(isar, ID_ISAR5, u);
- u = cpu->isar.id_isar6;
+ u = GET_IDREG(isar, ID_ISAR6);
u = FIELD_DP32(u, ID_ISAR6, DP, 0);
u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
u = FIELD_DP32(u, ID_ISAR6, I8MM, 0);
- cpu->isar.id_isar6 = u;
+ SET_IDREG(isar, ID_ISAR6, u);
if (!arm_feature(env, ARM_FEATURE_M)) {
u = cpu->isar.mvfr1;
@@ -2238,19 +2238,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
unset_feature(env, ARM_FEATURE_THUMB_DSP);
- u = cpu->isar.id_isar1;
- u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
- cpu->isar.id_isar1 = u;
+ FIELD_DP32_IDREG(isar, ID_ISAR1, EXTEND, 1);
- u = cpu->isar.id_isar2;
+ u = GET_IDREG(isar, ID_ISAR2);
u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
- cpu->isar.id_isar2 = u;
+ SET_IDREG(isar, ID_ISAR2, u);
- u = cpu->isar.id_isar3;
+ u = GET_IDREG(isar, ID_ISAR3);
u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
- cpu->isar.id_isar3 = u;
+ SET_IDREG(isar, ID_ISAR3, u);
}
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a3a3b8031eed..c98bdc1687c0 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1073,13 +1073,6 @@ struct ArchCPU {
* field by reading the value from the KVM vCPU.
*/
struct ARMISARegisters {
- uint32_t id_isar0;
- uint32_t id_isar1;
- uint32_t id_isar2;
- uint32_t id_isar3;
- uint32_t id_isar4;
- uint32_t id_isar5;
- uint32_t id_isar6;
uint32_t id_mmfr0;
uint32_t id_mmfr1;
uint32_t id_mmfr2;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index c8ab8761282a..1489ebb1015e 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -660,13 +660,13 @@ static void aarch64_a57_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_isar6 = 0;
+ SET_IDREG(isar, ID_ISAR0, 0x02101110);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232042);
+ SET_IDREG(isar, ID_ISAR3, 0x01112131);
+ SET_IDREG(isar, ID_ISAR4, 0x00011142);
+ SET_IDREG(isar, ID_ISAR5, 0x00011121);
+ SET_IDREG(isar, ID_ISAR6, 0);
SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
@@ -722,13 +722,13 @@ static void aarch64_a53_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_isar6 = 0;
+ SET_IDREG(isar, ID_ISAR0, 0x02101110);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232042);
+ SET_IDREG(isar, ID_ISAR3, 0x01112131);
+ SET_IDREG(isar, ID_ISAR4, 0x00011142);
+ SET_IDREG(isar, ID_ISAR5, 0x00011121);
+ SET_IDREG(isar, ID_ISAR6, 0);
SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 275e590876bf..1ba8551f6db8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7828,32 +7828,32 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_isar0 },
+ .resetvalue = GET_IDREG(isar, ID_ISAR0)},
{ .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_isar1 },
+ .resetvalue = GET_IDREG(isar, ID_ISAR1)},
{ .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_isar2 },
+ .resetvalue = GET_IDREG(isar, ID_ISAR2)},
{ .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_isar3 },
+ .resetvalue = GET_IDREG(isar, ID_ISAR3) },
{ .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_isar4 },
+ .resetvalue = GET_IDREG(isar, ID_ISAR4) },
{ .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_isar5 },
+ .resetvalue = GET_IDREG(isar, ID_ISAR5) },
{ .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
@@ -7863,7 +7863,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_isar6 },
+ .resetvalue = GET_IDREG(isar, ID_ISAR6) },
};
define_arm_cp_regs(cpu, v6_idregs);
define_arm_cp_regs(cpu, v6_cp_reginfo);
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index a73ff0a603bc..ceb7e7bec7a2 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -383,22 +383,15 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ARM64_SYS_REG(3, 0, 0, 1, 6));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
ARM64_SYS_REG(3, 0, 0, 1, 7));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
- ARM64_SYS_REG(3, 0, 0, 2, 0));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
- ARM64_SYS_REG(3, 0, 0, 2, 1));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
- ARM64_SYS_REG(3, 0, 0, 2, 2));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
- ARM64_SYS_REG(3, 0, 0, 2, 3));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
- ARM64_SYS_REG(3, 0, 0, 2, 4));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
- ARM64_SYS_REG(3, 0, 0, 2, 5));
+ err |= get_host_cpu_reg(fd, ahcf, ID_ISAR0_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_ISAR1_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_ISAR2_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_ISAR3_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_ISAR4_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_ISAR5_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_ISAR6_EL1_IDX);
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
ARM64_SYS_REG(3, 0, 0, 2, 6));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
- ARM64_SYS_REG(3, 0, 0, 2, 7));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
ARM64_SYS_REG(3, 0, 0, 3, 0));
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index c4dd30927268..9d5938abdb4b 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -45,6 +45,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
static void cortex_m0_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_M);
@@ -66,18 +67,19 @@ static void cortex_m0_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x00000000;
cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01141110;
- cpu->isar.id_isar1 = 0x02111000;
- cpu->isar.id_isar2 = 0x21112231;
- cpu->isar.id_isar3 = 0x01111110;
- cpu->isar.id_isar4 = 0x01310102;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
+ SET_IDREG(idregs, ID_ISAR0, 0x01141110);
+ SET_IDREG(idregs, ID_ISAR1, 0x02111000);
+ SET_IDREG(idregs, ID_ISAR2, 0x21112231);
+ SET_IDREG(idregs, ID_ISAR3, 0x01111110);
+ SET_IDREG(idregs, ID_ISAR4, 0x01310102);
+ SET_IDREG(idregs, ID_ISAR5, 0x00000000);
+ SET_IDREG(idregs, ID_ISAR6, 0x00000000);
}
static void cortex_m3_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_M);
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
@@ -91,18 +93,19 @@ static void cortex_m3_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x00000000;
cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01141110;
- cpu->isar.id_isar1 = 0x02111000;
- cpu->isar.id_isar2 = 0x21112231;
- cpu->isar.id_isar3 = 0x01111110;
- cpu->isar.id_isar4 = 0x01310102;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
+ SET_IDREG(idregs, ID_ISAR0, 0x01141110);
+ SET_IDREG(idregs, ID_ISAR1, 0x02111000);
+ SET_IDREG(idregs, ID_ISAR2, 0x21112231);
+ SET_IDREG(idregs, ID_ISAR3, 0x01111110);
+ SET_IDREG(idregs, ID_ISAR4, 0x01310102);
+ SET_IDREG(idregs, ID_ISAR5, 0x00000000);
+ SET_IDREG(idregs, ID_ISAR6, 0x00000000);
}
static void cortex_m4_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_M);
@@ -121,18 +124,19 @@ static void cortex_m4_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x00000000;
cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01141110;
- cpu->isar.id_isar1 = 0x02111000;
- cpu->isar.id_isar2 = 0x21112231;
- cpu->isar.id_isar3 = 0x01111110;
- cpu->isar.id_isar4 = 0x01310102;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
+ SET_IDREG(idregs, ID_ISAR0, 0x01141110);
+ SET_IDREG(idregs, ID_ISAR1, 0x02111000);
+ SET_IDREG(idregs, ID_ISAR2, 0x21112231);
+ SET_IDREG(idregs, ID_ISAR3, 0x01111110);
+ SET_IDREG(idregs, ID_ISAR4, 0x01310102);
+ SET_IDREG(idregs, ID_ISAR5, 0x00000000);
+ SET_IDREG(idregs, ID_ISAR6, 0x00000000);
}
static void cortex_m7_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_M);
@@ -151,18 +155,19 @@ static void cortex_m7_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x01000000;
cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01101110;
- cpu->isar.id_isar1 = 0x02112000;
- cpu->isar.id_isar2 = 0x20232231;
- cpu->isar.id_isar3 = 0x01111131;
- cpu->isar.id_isar4 = 0x01310132;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
+ SET_IDREG(idregs, ID_ISAR0, 0x01101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x02112000);
+ SET_IDREG(idregs, ID_ISAR2, 0x20232231);
+ SET_IDREG(idregs, ID_ISAR3, 0x01111131);
+ SET_IDREG(idregs, ID_ISAR4, 0x01310132);
+ SET_IDREG(idregs, ID_ISAR5, 0x00000000);
+ SET_IDREG(idregs, ID_ISAR6, 0x00000000);
}
static void cortex_m33_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_M);
@@ -183,13 +188,13 @@ static void cortex_m33_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x01000000;
cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01101110;
- cpu->isar.id_isar1 = 0x02212000;
- cpu->isar.id_isar2 = 0x20232232;
- cpu->isar.id_isar3 = 0x01111131;
- cpu->isar.id_isar4 = 0x01310132;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
+ SET_IDREG(idregs, ID_ISAR0, 0x01101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x02212000);
+ SET_IDREG(idregs, ID_ISAR2, 0x20232232);
+ SET_IDREG(idregs, ID_ISAR3, 0x01111131);
+ SET_IDREG(idregs, ID_ISAR4, 0x01310132);
+ SET_IDREG(idregs, ID_ISAR5, 0x00000000);
+ SET_IDREG(idregs, ID_ISAR6, 0x00000000);
cpu->clidr = 0x00000000;
cpu->ctr = 0x8000c000;
}
@@ -197,6 +202,7 @@ static void cortex_m33_initfn(Object *obj)
static void cortex_m55_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_V8_1M);
@@ -220,13 +226,13 @@ static void cortex_m55_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x01000000;
cpu->isar.id_mmfr3 = 0x00000011;
- cpu->isar.id_isar0 = 0x01103110;
- cpu->isar.id_isar1 = 0x02212000;
- cpu->isar.id_isar2 = 0x20232232;
- cpu->isar.id_isar3 = 0x01111131;
- cpu->isar.id_isar4 = 0x01310132;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
+ SET_IDREG(idregs, ID_ISAR0, 0x01103110);
+ SET_IDREG(idregs, ID_ISAR1, 0x02212000);
+ SET_IDREG(idregs, ID_ISAR2, 0x20232232);
+ SET_IDREG(idregs, ID_ISAR3, 0x01111131);
+ SET_IDREG(idregs, ID_ISAR4, 0x01310132);
+ SET_IDREG(idregs, ID_ISAR5, 0x00000000);
+ SET_IDREG(idregs, ID_ISAR6, 0x00000000);
cpu->clidr = 0x00000000; /* caches not implemented */
cpu->ctr = 0x8303c003;
}
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 2c45b7eddda7..d022ba3c9b32 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -23,18 +23,19 @@
void aa32_max_features(ARMCPU *cpu)
{
uint32_t t;
+ ARMISARegisters *isar = &cpu->isar;
/* Add additional features supported by QEMU */
- t = cpu->isar.id_isar5;
+ t = GET_IDREG(isar, ID_ISAR5);
t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
- cpu->isar.id_isar5 = t;
+ SET_IDREG(isar, ID_ISAR5, t);
- t = cpu->isar.id_isar6;
+ t = GET_IDREG(isar, ID_ISAR6);
t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
@@ -42,7 +43,7 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
- cpu->isar.id_isar6 = t;
+ SET_IDREG(isar, ID_ISAR6, t);
t = cpu->isar.mvfr1;
t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
@@ -140,7 +141,7 @@ static void arm926_initfn(Object *obj)
* ARMv5 does not have the ID_ISAR registers, but we can still
* set the field to indicate Jazelle support within QEMU.
*/
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
+ FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1);
/*
* Similarly, we need to set MVFR0 fields to enable vfp and short vector
* support even though ARMv5 doesn't have this register.
@@ -182,7 +183,7 @@ static void arm1026_initfn(Object *obj)
* ARMv5 does not have the ID_ISAR registers, but we can still
* set the field to indicate Jazelle support within QEMU.
*/
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
+ FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1);
/*
* Similarly, we need to set MVFR0 fields to enable vfp and short vector
* support even though ARMv5 doesn't have this register.
@@ -206,6 +207,7 @@ static void arm1026_initfn(Object *obj)
static void arm1136_r2_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
/*
* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
* older core than plain "arm1136". In particular this does not
@@ -233,17 +235,18 @@ static void arm1136_r2_initfn(Object *obj)
cpu->isar.id_mmfr0 = 0x01130003;
cpu->isar.id_mmfr1 = 0x10030302;
cpu->isar.id_mmfr2 = 0x01222110;
- cpu->isar.id_isar0 = 0x00140011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11231111;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x141;
+ SET_IDREG(isar, ID_ISAR0, 0x00140011);
+ SET_IDREG(isar, ID_ISAR1, 0x12002111);
+ SET_IDREG(isar, ID_ISAR2, 0x11231111);
+ SET_IDREG(isar, ID_ISAR3, 0x01102131);
+ SET_IDREG(isar, ID_ISAR4, 0x141);
cpu->reset_auxcr = 7;
}
static void arm1136_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,arm1136";
set_feature(&cpu->env, ARM_FEATURE_V6K);
@@ -264,17 +267,18 @@ static void arm1136_initfn(Object *obj)
cpu->isar.id_mmfr0 = 0x01130003;
cpu->isar.id_mmfr1 = 0x10030302;
cpu->isar.id_mmfr2 = 0x01222110;
- cpu->isar.id_isar0 = 0x00140011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11231111;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x141;
+ SET_IDREG(isar, ID_ISAR0, 0x00140011);
+ SET_IDREG(isar, ID_ISAR1, 0x12002111);
+ SET_IDREG(isar, ID_ISAR2, 0x11231111);
+ SET_IDREG(isar, ID_ISAR3, 0x01102131);
+ SET_IDREG(isar, ID_ISAR4, 0x141);
cpu->reset_auxcr = 7;
}
static void arm1176_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,arm1176";
set_feature(&cpu->env, ARM_FEATURE_V6K);
@@ -296,17 +300,18 @@ static void arm1176_initfn(Object *obj)
cpu->isar.id_mmfr0 = 0x01130003;
cpu->isar.id_mmfr1 = 0x10030302;
cpu->isar.id_mmfr2 = 0x01222100;
- cpu->isar.id_isar0 = 0x0140011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11231121;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x01141;
+ SET_IDREG(isar, ID_ISAR0, 0x0140011);
+ SET_IDREG(isar, ID_ISAR1, 0x12002111);
+ SET_IDREG(isar, ID_ISAR2, 0x11231121);
+ SET_IDREG(isar, ID_ISAR3, 0x01102131);
+ SET_IDREG(isar, ID_ISAR4, 0x01141);
cpu->reset_auxcr = 7;
}
static void arm11mpcore_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,arm11mpcore";
set_feature(&cpu->env, ARM_FEATURE_V6K);
@@ -325,11 +330,11 @@ static void arm11mpcore_initfn(Object *obj)
cpu->isar.id_mmfr0 = 0x01100103;
cpu->isar.id_mmfr1 = 0x10020302;
cpu->isar.id_mmfr2 = 0x01222000;
- cpu->isar.id_isar0 = 0x00100011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11221011;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x141;
+ SET_IDREG(isar, ID_ISAR0, 0x00100011);
+ SET_IDREG(isar, ID_ISAR1, 0x12002111);
+ SET_IDREG(isar, ID_ISAR2, 0x11221011);
+ SET_IDREG(isar, ID_ISAR3, 0x01102131);
+ SET_IDREG(isar, ID_ISAR4, 0x141);
cpu->reset_auxcr = 1;
}
@@ -343,6 +348,7 @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
static void cortex_a8_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,cortex-a8";
set_feature(&cpu->env, ARM_FEATURE_V7);
@@ -365,11 +371,11 @@ static void cortex_a8_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x20000000;
cpu->isar.id_mmfr2 = 0x01202000;
cpu->isar.id_mmfr3 = 0x11;
- cpu->isar.id_isar0 = 0x00101111;
- cpu->isar.id_isar1 = 0x12112111;
- cpu->isar.id_isar2 = 0x21232031;
- cpu->isar.id_isar3 = 0x11112131;
- cpu->isar.id_isar4 = 0x00111142;
+ SET_IDREG(isar, ID_ISAR0, 0x00101111);
+ SET_IDREG(isar, ID_ISAR1, 0x12112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232031);
+ SET_IDREG(isar, ID_ISAR3, 0x11112131);
+ SET_IDREG(isar, ID_ISAR4, 0x00111142);
cpu->isar.dbgdidr = 0x15141000;
cpu->clidr = (1 << 27) | (2 << 24) | 3;
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
@@ -412,6 +418,7 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
static void cortex_a9_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,cortex-a9";
set_feature(&cpu->env, ARM_FEATURE_V7);
@@ -440,11 +447,11 @@ static void cortex_a9_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x20000000;
cpu->isar.id_mmfr2 = 0x01230000;
cpu->isar.id_mmfr3 = 0x00002111;
- cpu->isar.id_isar0 = 0x00101111;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232041;
- cpu->isar.id_isar3 = 0x11112131;
- cpu->isar.id_isar4 = 0x00111142;
+ SET_IDREG(isar, ID_ISAR0, 0x00101111);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232041);
+ SET_IDREG(isar, ID_ISAR3, 0x11112131);
+ SET_IDREG(isar, ID_ISAR4, 0x00111142);
cpu->isar.dbgdidr = 0x35141000;
cpu->clidr = (1 << 27) | (1 << 24) | 3;
cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
@@ -479,6 +486,7 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
static void cortex_a7_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,cortex-a7";
set_feature(&cpu->env, ARM_FEATURE_V7VE);
@@ -509,11 +517,11 @@ static void cortex_a7_initfn(Object *obj)
* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
* table 4-41 gives 0x02101110, which includes the arm div insns.
*/
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232041;
- cpu->isar.id_isar3 = 0x11112131;
- cpu->isar.id_isar4 = 0x10011142;
+ SET_IDREG(isar, ID_ISAR0, 0x02101110);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232041);
+ SET_IDREG(isar, ID_ISAR3, 0x11112131);
+ SET_IDREG(isar, ID_ISAR4, 0x10011142);
cpu->isar.dbgdidr = 0x3515f005;
cpu->isar.dbgdevid = 0x01110f13;
cpu->isar.dbgdevid1 = 0x1;
@@ -528,6 +536,7 @@ static void cortex_a7_initfn(Object *obj)
static void cortex_a15_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
cpu->dtb_compatible = "arm,cortex-a15";
set_feature(&cpu->env, ARM_FEATURE_V7VE);
@@ -556,11 +565,11 @@ static void cortex_a15_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x20000000;
cpu->isar.id_mmfr2 = 0x01240000;
cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232041;
- cpu->isar.id_isar3 = 0x11112131;
- cpu->isar.id_isar4 = 0x10011142;
+ SET_IDREG(isar, ID_ISAR0, 0x02101110);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232041);
+ SET_IDREG(isar, ID_ISAR3, 0x11112131);
+ SET_IDREG(isar, ID_ISAR4, 0x10011142);
cpu->isar.dbgdidr = 0x3515f021;
cpu->isar.dbgdevid = 0x01110f13;
cpu->isar.dbgdevid1 = 0x0;
@@ -585,6 +594,7 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
static void cortex_r5_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_V7MP);
@@ -599,13 +609,13 @@ static void cortex_r5_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x01200000;
cpu->isar.id_mmfr3 = 0x0211;
- cpu->isar.id_isar0 = 0x02101111;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232141;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x0010142;
- cpu->isar.id_isar5 = 0x0;
- cpu->isar.id_isar6 = 0x0;
+ SET_IDREG(isar, ID_ISAR0, 0x02101111);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232141);
+ SET_IDREG(isar, ID_ISAR3, 0x01112131);
+ SET_IDREG(isar, ID_ISAR4, 0x0010142);
+ SET_IDREG(isar, ID_ISAR5, 0x21232141);
+ SET_IDREG(isar, ID_ISAR6, 0x0);
cpu->mp_is_up = true;
cpu->pmsav7_dregion = 16;
cpu->isar.reset_pmcr_el0 = 0x41151800;
@@ -720,6 +730,7 @@ static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
static void cortex_r52_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -746,12 +757,12 @@ static void cortex_r52_initfn(Object *obj)
cpu->isar.id_mmfr2 = 0x01200000;
cpu->isar.id_mmfr3 = 0xf0102211;
cpu->isar.id_mmfr4 = 0x00000010;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232142;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x00010001;
+ SET_IDREG(isar, ID_ISAR0, 0x02101110);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232142);
+ SET_IDREG(isar, ID_ISAR3, 0x01112131);
+ SET_IDREG(isar, ID_ISAR4, 0x00010142);
+ SET_IDREG(isar, ID_ISAR5, 0x00010001);
cpu->isar.dbgdidr = 0x77168000;
cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
@@ -949,6 +960,7 @@ static void pxa270c5_initfn(Object *obj)
static void arm_max_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ ARMISARegisters *isar = &cpu->isar;
/* aarch64_a57_initfn, advertising none of the aarch64 features */
cpu->dtb_compatible = "arm,cortex-a57";
@@ -976,13 +988,13 @@ static void arm_max_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_isar6 = 0;
+ SET_IDREG(isar, ID_ISAR0, 0x02101110);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232042);
+ SET_IDREG(isar, ID_ISAR3, 0x01112131);
+ SET_IDREG(isar, ID_ISAR4, 0x00011142);
+ SET_IDREG(isar, ID_ISAR5, 0x00011121);
+ SET_IDREG(isar, ID_ISAR6, 0);
cpu->isar.reset_pmcr_el0 = 0x41013000;
cpu->clidr = 0x0a200023;
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index cadc1258fc40..ad47279cdd46 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -57,12 +57,12 @@ static void aarch64_a35_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
+ SET_IDREG(isar, ID_ISAR0, 0x02101110);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232042);
+ SET_IDREG(isar, ID_ISAR3, 0x01112131);
+ SET_IDREG(isar, ID_ISAR4, 0x00011142);
+ SET_IDREG(isar, ID_ISAR5, 0x00011121);
SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
SET_IDREG(isar, ID_AA64PFR1, 0);
SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
@@ -229,13 +229,13 @@ static void aarch64_a55_initfn(Object *obj)
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x04010088;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x01011121;
- cpu->isar.id_isar6 = 0x00000010;
+ SET_IDREG(isar, ID_ISAR0, 0x02101110);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232042);
+ SET_IDREG(isar, ID_ISAR3, 0x01112131);
+ SET_IDREG(isar, ID_ISAR4, 0x00011142);
+ SET_IDREG(isar, ID_ISAR5, 0x01011121);
+ SET_IDREG(isar, ID_ISAR6, 0x00000010);
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
@@ -303,12 +303,12 @@ static void aarch64_a72_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
+ SET_IDREG(isar, ID_ISAR0, 0x02101110);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232042);
+ SET_IDREG(isar, ID_ISAR3, 0x01112131);
+ SET_IDREG(isar, ID_ISAR4, 0x00011142);
+ SET_IDREG(isar, ID_ISAR5, 0x00011121);
SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
@@ -362,13 +362,13 @@ static void aarch64_a76_initfn(Object *obj)
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x04010088;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x01011121;
- cpu->isar.id_isar6 = 0x00000010;
+ SET_IDREG(isar, ID_ISAR0, 0x02101110);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232042);
+ SET_IDREG(isar, ID_ISAR3, 0x01112131);
+ SET_IDREG(isar, ID_ISAR4, 0x00010142);
+ SET_IDREG(isar, ID_ISAR5, 0x01011121);
+ SET_IDREG(isar, ID_ISAR6, 0x00000010);
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
@@ -610,13 +610,13 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x04010088;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x01011121;
- cpu->isar.id_isar6 = 0x00000010;
+ SET_IDREG(isar, ID_ISAR0, 0x02101110);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232042);
+ SET_IDREG(isar, ID_ISAR3, 0x01112131);
+ SET_IDREG(isar, ID_ISAR4, 0x00010142);
+ SET_IDREG(isar, ID_ISAR5, 0x01011121);
+ SET_IDREG(isar, ID_ISAR6, 0x00000010);
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
@@ -689,13 +689,13 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x15011099;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x11011121;
- cpu->isar.id_isar6 = 0x01100111;
+ SET_IDREG(isar, ID_ISAR0, 0x02101110);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232042);
+ SET_IDREG(isar, ID_ISAR3, 0x01112131);
+ SET_IDREG(isar, ID_ISAR4, 0x00010142);
+ SET_IDREG(isar, ID_ISAR5, 0x11011121);
+ SET_IDREG(isar, ID_ISAR6, 0x01100111);
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
@@ -910,14 +910,14 @@ static void aarch64_a710_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x11011121; /* with Crypto */
+ SET_IDREG(isar, ID_ISAR0, 0x02101110);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232042);
+ SET_IDREG(isar, ID_ISAR3, 0x01112131);
+ SET_IDREG(isar, ID_ISAR4, 0x00010142);
+ SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */
cpu->isar.id_mmfr4 = 0x21021110;
- cpu->isar.id_isar6 = 0x01111111;
+ SET_IDREG(isar, ID_ISAR6, 0x01111111);
cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043;
@@ -1013,14 +1013,14 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x11011121; /* with Crypto */
+ SET_IDREG(isar, ID_ISAR0, 0x02101110);
+ SET_IDREG(isar, ID_ISAR1, 0x13112111);
+ SET_IDREG(isar, ID_ISAR2, 0x21232042);
+ SET_IDREG(isar, ID_ISAR3, 0x01112131);
+ SET_IDREG(isar, ID_ISAR4, 0x00010142);
+ SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */
cpu->isar.id_mmfr4 = 0x01021110;
- cpu->isar.id_isar6 = 0x01111111;
+ SET_IDREG(isar, ID_ISAR6, 0x01111111);
cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043;
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH for-10.1 v5 08/13] arm/cpu: Store id_isar0-7 into the idregs array
2025-04-09 14:42 ` [PATCH for-10.1 v5 08/13] arm/cpu: Store id_isar0-7 " Cornelia Huck
@ 2025-04-28 16:04 ` Eric Auger
2025-04-29 9:51 ` Cornelia Huck
0 siblings, 1 reply; 29+ messages in thread
From: Eric Auger @ 2025-04-28 16:04 UTC (permalink / raw)
To: Cornelia Huck, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini
On 4/9/25 4:42 PM, Cornelia Huck wrote:
> From: Eric Auger <eric.auger@redhat.com>
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Sebastian Ott <sebott@redhat.com>
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
> ---
> hw/intc/armv7m_nvic.c | 12 ++--
> target/arm/cpu-features.h | 36 +++++-----
> target/arm/cpu.c | 24 +++----
> target/arm/cpu.h | 7 --
> target/arm/cpu64.c | 28 ++++----
> target/arm/helper.c | 14 ++--
> target/arm/kvm.c | 21 ++----
> target/arm/tcg/cpu-v7m.c | 90 +++++++++++++-----------
> target/arm/tcg/cpu32.c | 144 +++++++++++++++++++++-----------------
> target/arm/tcg/cpu64.c | 108 ++++++++++++++--------------
> 10 files changed, 243 insertions(+), 241 deletions(-)
>
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index 7212c87c68ec..55e726be7a2c 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -1303,32 +1303,32 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
> if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
> goto bad_offset;
> }
> - return cpu->isar.id_isar0;
> + return GET_IDREG(&cpu->isar, ID_ISAR0);
> case 0xd64: /* ISAR1. */
> if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
> goto bad_offset;
> }
> - return cpu->isar.id_isar1;
> + return GET_IDREG(&cpu->isar, ID_ISAR1);
> case 0xd68: /* ISAR2. */
> if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
> goto bad_offset;
> }
> - return cpu->isar.id_isar2;
> + return GET_IDREG(&cpu->isar, ID_ISAR2);
> case 0xd6c: /* ISAR3. */
> if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
> goto bad_offset;
> }
> - return cpu->isar.id_isar3;
> + return GET_IDREG(&cpu->isar, ID_ISAR3);
> case 0xd70: /* ISAR4. */
> if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
> goto bad_offset;
> }
> - return cpu->isar.id_isar4;
> + return GET_IDREG(&cpu->isar, ID_ISAR4);
> case 0xd74: /* ISAR5. */
> if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
> goto bad_offset;
> }
> - return cpu->isar.id_isar5;
> + return GET_IDREG(&cpu->isar, ID_ISAR5);
> case 0xd78: /* CLIDR */
> return cpu->clidr;
> case 0xd7c: /* CTR */
> diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
> index 1ac1f3e95984..003cf735e8ef 100644
> --- a/target/arm/cpu-features.h
> +++ b/target/arm/cpu-features.h
> @@ -45,93 +45,93 @@
> */
> static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
> + return FIELD_EX32_IDREG(id, ID_ISAR0, DIVIDE) != 0;
> }
>
> static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
> + return FIELD_EX32_IDREG(id, ID_ISAR0, DIVIDE) > 1;
> }
>
> static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
> {
> /* (M-profile) low-overhead loops and branch future */
> - return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
> + return FIELD_EX32_IDREG(id, ID_ISAR0, CMPBRANCH) >= 3;
> }
>
> static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
> + return FIELD_EX32_IDREG(id, ID_ISAR1, JAZELLE) != 0;
> }
>
> static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
> + return FIELD_EX32_IDREG(id, ID_ISAR5, AES) != 0;
> }
>
> static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
> + return FIELD_EX32_IDREG(id, ID_ISAR5, AES) > 1;
> }
>
> static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
> + return FIELD_EX32_IDREG(id, ID_ISAR5, SHA1) != 0;
> }
>
> static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
> + return FIELD_EX32_IDREG(id, ID_ISAR5, SHA2) != 0;
> }
>
> static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
> + return FIELD_EX32_IDREG(id, ID_ISAR5, CRC32) != 0;
> }
>
> static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
> + return FIELD_EX32_IDREG(id, ID_ISAR5, RDM) != 0;
> }
>
> static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
> + return FIELD_EX32_IDREG(id, ID_ISAR5, VCMA) != 0;
> }
>
> static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
> + return FIELD_EX32_IDREG(id, ID_ISAR6, JSCVT) != 0;
> }
>
> static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
> + return FIELD_EX32_IDREG(id, ID_ISAR6, DP) != 0;
> }
>
> static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
> + return FIELD_EX32_IDREG(id, ID_ISAR6, FHM) != 0;
> }
>
> static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
> + return FIELD_EX32_IDREG(id, ID_ISAR6, SB) != 0;
> }
>
> static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
> + return FIELD_EX32_IDREG(id, ID_ISAR6, SPECRES) != 0;
> }
>
> static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0;
> + return FIELD_EX32_IDREG(id, ID_ISAR6, BF16) != 0;
> }
>
> static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
> {
> - return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0;
> + return FIELD_EX32_IDREG(id, ID_ISAR6, I8MM) != 0;
> }
>
> static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 7bd20d1f2710..45d922110c17 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2132,10 +2132,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
>
> FIELD_DP64_IDREG(isar, ID_AA64PFR0, FP, 0xf);
>
> - u = cpu->isar.id_isar6;
> + u = GET_IDREG(isar, ID_ISAR6);
> u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
> u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
> - cpu->isar.id_isar6 = u;
> + SET_IDREG(isar, ID_ISAR6, u);
>
> u = cpu->isar.mvfr0;
> u = FIELD_DP32(u, MVFR0, FPSP, 0);
> @@ -2187,20 +2187,20 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
>
> FIELD_DP64_IDREG(isar, ID_AA64PFR0, ADVSIMD, 0xf);
>
> - u = cpu->isar.id_isar5;
> + u = GET_IDREG(isar, ID_ISAR5);
> u = FIELD_DP32(u, ID_ISAR5, AES, 0);
> u = FIELD_DP32(u, ID_ISAR5, SHA1, 0);
> u = FIELD_DP32(u, ID_ISAR5, SHA2, 0);
> u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
> u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
> - cpu->isar.id_isar5 = u;
> + SET_IDREG(isar, ID_ISAR5, u);
>
> - u = cpu->isar.id_isar6;
> + u = GET_IDREG(isar, ID_ISAR6);
> u = FIELD_DP32(u, ID_ISAR6, DP, 0);
> u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
> u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
> u = FIELD_DP32(u, ID_ISAR6, I8MM, 0);
> - cpu->isar.id_isar6 = u;
> + SET_IDREG(isar, ID_ISAR6, u);
>
> if (!arm_feature(env, ARM_FEATURE_M)) {
> u = cpu->isar.mvfr1;
> @@ -2238,19 +2238,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
>
> unset_feature(env, ARM_FEATURE_THUMB_DSP);
>
> - u = cpu->isar.id_isar1;
> - u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
> - cpu->isar.id_isar1 = u;
> + FIELD_DP32_IDREG(isar, ID_ISAR1, EXTEND, 1);
>
> - u = cpu->isar.id_isar2;
> + u = GET_IDREG(isar, ID_ISAR2);
> u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
> u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
> - cpu->isar.id_isar2 = u;
> + SET_IDREG(isar, ID_ISAR2, u);
>
> - u = cpu->isar.id_isar3;
> + u = GET_IDREG(isar, ID_ISAR3);
> u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
> u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
> - cpu->isar.id_isar3 = u;
> + SET_IDREG(isar, ID_ISAR3, u);
> }
>
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index a3a3b8031eed..c98bdc1687c0 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1073,13 +1073,6 @@ struct ArchCPU {
> * field by reading the value from the KVM vCPU.
> */
> struct ARMISARegisters {
> - uint32_t id_isar0;
> - uint32_t id_isar1;
> - uint32_t id_isar2;
> - uint32_t id_isar3;
> - uint32_t id_isar4;
> - uint32_t id_isar5;
> - uint32_t id_isar6;
> uint32_t id_mmfr0;
> uint32_t id_mmfr1;
> uint32_t id_mmfr2;
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index c8ab8761282a..1489ebb1015e 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -660,13 +660,13 @@ static void aarch64_a57_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x40000000;
> cpu->isar.id_mmfr2 = 0x01260000;
> cpu->isar.id_mmfr3 = 0x02102211;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00011142;
> - cpu->isar.id_isar5 = 0x00011121;
> - cpu->isar.id_isar6 = 0;
> + SET_IDREG(isar, ID_ISAR0, 0x02101110);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232042);
> + SET_IDREG(isar, ID_ISAR3, 0x01112131);
> + SET_IDREG(isar, ID_ISAR4, 0x00011142);
> + SET_IDREG(isar, ID_ISAR5, 0x00011121);
> + SET_IDREG(isar, ID_ISAR6, 0);
> SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
> SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> @@ -722,13 +722,13 @@ static void aarch64_a53_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x40000000;
> cpu->isar.id_mmfr2 = 0x01260000;
> cpu->isar.id_mmfr3 = 0x02102211;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00011142;
> - cpu->isar.id_isar5 = 0x00011121;
> - cpu->isar.id_isar6 = 0;
> + SET_IDREG(isar, ID_ISAR0, 0x02101110);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232042);
> + SET_IDREG(isar, ID_ISAR3, 0x01112131);
> + SET_IDREG(isar, ID_ISAR4, 0x00011142);
> + SET_IDREG(isar, ID_ISAR5, 0x00011121);
> + SET_IDREG(isar, ID_ISAR6, 0);
> SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
> SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 275e590876bf..1ba8551f6db8 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -7828,32 +7828,32 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa32_tid3,
> - .resetvalue = cpu->isar.id_isar0 },
> + .resetvalue = GET_IDREG(isar, ID_ISAR0)},
> { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa32_tid3,
> - .resetvalue = cpu->isar.id_isar1 },
> + .resetvalue = GET_IDREG(isar, ID_ISAR1)},
> { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa32_tid3,
> - .resetvalue = cpu->isar.id_isar2 },
> + .resetvalue = GET_IDREG(isar, ID_ISAR2)},
> { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa32_tid3,
> - .resetvalue = cpu->isar.id_isar3 },
> + .resetvalue = GET_IDREG(isar, ID_ISAR3) },
> { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa32_tid3,
> - .resetvalue = cpu->isar.id_isar4 },
> + .resetvalue = GET_IDREG(isar, ID_ISAR4) },
> { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa32_tid3,
> - .resetvalue = cpu->isar.id_isar5 },
> + .resetvalue = GET_IDREG(isar, ID_ISAR5) },
> { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
> .access = PL1_R, .type = ARM_CP_CONST,
> @@ -7863,7 +7863,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
> .access = PL1_R, .type = ARM_CP_CONST,
> .accessfn = access_aa32_tid3,
> - .resetvalue = cpu->isar.id_isar6 },
> + .resetvalue = GET_IDREG(isar, ID_ISAR6) },
> };
> define_arm_cp_regs(cpu, v6_idregs);
> define_arm_cp_regs(cpu, v6_cp_reginfo);
> diff --git a/target/arm/kvm.c b/target/arm/kvm.c
> index a73ff0a603bc..ceb7e7bec7a2 100644
> --- a/target/arm/kvm.c
> +++ b/target/arm/kvm.c
> @@ -383,22 +383,15 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> ARM64_SYS_REG(3, 0, 0, 1, 6));
> err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
> ARM64_SYS_REG(3, 0, 0, 1, 7));
> - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
> - ARM64_SYS_REG(3, 0, 0, 2, 0));
> - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
> - ARM64_SYS_REG(3, 0, 0, 2, 1));
> - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
> - ARM64_SYS_REG(3, 0, 0, 2, 2));
> - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
> - ARM64_SYS_REG(3, 0, 0, 2, 3));
> - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
> - ARM64_SYS_REG(3, 0, 0, 2, 4));
> - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
> - ARM64_SYS_REG(3, 0, 0, 2, 5));
> + err |= get_host_cpu_reg(fd, ahcf, ID_ISAR0_EL1_IDX);
> + err |= get_host_cpu_reg(fd, ahcf, ID_ISAR1_EL1_IDX);
> + err |= get_host_cpu_reg(fd, ahcf, ID_ISAR2_EL1_IDX);
> + err |= get_host_cpu_reg(fd, ahcf, ID_ISAR3_EL1_IDX);
> + err |= get_host_cpu_reg(fd, ahcf, ID_ISAR4_EL1_IDX);
> + err |= get_host_cpu_reg(fd, ahcf, ID_ISAR5_EL1_IDX);
> + err |= get_host_cpu_reg(fd, ahcf, ID_ISAR6_EL1_IDX);
> err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
> ARM64_SYS_REG(3, 0, 0, 2, 6));
> - err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
> - ARM64_SYS_REG(3, 0, 0, 2, 7));
>
> err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
> ARM64_SYS_REG(3, 0, 0, 3, 0));
> diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
> index c4dd30927268..9d5938abdb4b 100644
> --- a/target/arm/tcg/cpu-v7m.c
> +++ b/target/arm/tcg/cpu-v7m.c
> @@ -45,6 +45,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
> static void cortex_m0_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + uint64_t *idregs = cpu->isar.idregs;
> set_feature(&cpu->env, ARM_FEATURE_V6);
> set_feature(&cpu->env, ARM_FEATURE_M);
>
> @@ -66,18 +67,19 @@ static void cortex_m0_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x00000000;
> cpu->isar.id_mmfr2 = 0x00000000;
> cpu->isar.id_mmfr3 = 0x00000000;
> - cpu->isar.id_isar0 = 0x01141110;
> - cpu->isar.id_isar1 = 0x02111000;
> - cpu->isar.id_isar2 = 0x21112231;
> - cpu->isar.id_isar3 = 0x01111110;
> - cpu->isar.id_isar4 = 0x01310102;
> - cpu->isar.id_isar5 = 0x00000000;
> - cpu->isar.id_isar6 = 0x00000000;
> + SET_IDREG(idregs, ID_ISAR0, 0x01141110);
> + SET_IDREG(idregs, ID_ISAR1, 0x02111000);
> + SET_IDREG(idregs, ID_ISAR2, 0x21112231);
> + SET_IDREG(idregs, ID_ISAR3, 0x01111110);
> + SET_IDREG(idregs, ID_ISAR4, 0x01310102);
> + SET_IDREG(idregs, ID_ISAR5, 0x00000000);
> + SET_IDREG(idregs, ID_ISAR6, 0x00000000);
> }
>
> static void cortex_m3_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + uint64_t *idregs = cpu->isar.idregs;
> set_feature(&cpu->env, ARM_FEATURE_V7);
> set_feature(&cpu->env, ARM_FEATURE_M);
> set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
> @@ -91,18 +93,19 @@ static void cortex_m3_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x00000000;
> cpu->isar.id_mmfr2 = 0x00000000;
> cpu->isar.id_mmfr3 = 0x00000000;
> - cpu->isar.id_isar0 = 0x01141110;
> - cpu->isar.id_isar1 = 0x02111000;
> - cpu->isar.id_isar2 = 0x21112231;
> - cpu->isar.id_isar3 = 0x01111110;
> - cpu->isar.id_isar4 = 0x01310102;
> - cpu->isar.id_isar5 = 0x00000000;
> - cpu->isar.id_isar6 = 0x00000000;
> + SET_IDREG(idregs, ID_ISAR0, 0x01141110);
> + SET_IDREG(idregs, ID_ISAR1, 0x02111000);
> + SET_IDREG(idregs, ID_ISAR2, 0x21112231);
> + SET_IDREG(idregs, ID_ISAR3, 0x01111110);
> + SET_IDREG(idregs, ID_ISAR4, 0x01310102);
> + SET_IDREG(idregs, ID_ISAR5, 0x00000000);
> + SET_IDREG(idregs, ID_ISAR6, 0x00000000);
> }
>
> static void cortex_m4_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + uint64_t *idregs = cpu->isar.idregs;
>
> set_feature(&cpu->env, ARM_FEATURE_V7);
> set_feature(&cpu->env, ARM_FEATURE_M);
> @@ -121,18 +124,19 @@ static void cortex_m4_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x00000000;
> cpu->isar.id_mmfr2 = 0x00000000;
> cpu->isar.id_mmfr3 = 0x00000000;
> - cpu->isar.id_isar0 = 0x01141110;
> - cpu->isar.id_isar1 = 0x02111000;
> - cpu->isar.id_isar2 = 0x21112231;
> - cpu->isar.id_isar3 = 0x01111110;
> - cpu->isar.id_isar4 = 0x01310102;
> - cpu->isar.id_isar5 = 0x00000000;
> - cpu->isar.id_isar6 = 0x00000000;
> + SET_IDREG(idregs, ID_ISAR0, 0x01141110);
> + SET_IDREG(idregs, ID_ISAR1, 0x02111000);
> + SET_IDREG(idregs, ID_ISAR2, 0x21112231);
> + SET_IDREG(idregs, ID_ISAR3, 0x01111110);
> + SET_IDREG(idregs, ID_ISAR4, 0x01310102);
> + SET_IDREG(idregs, ID_ISAR5, 0x00000000);
> + SET_IDREG(idregs, ID_ISAR6, 0x00000000);
> }
>
> static void cortex_m7_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + uint64_t *idregs = cpu->isar.idregs;
>
> set_feature(&cpu->env, ARM_FEATURE_V7);
> set_feature(&cpu->env, ARM_FEATURE_M);
> @@ -151,18 +155,19 @@ static void cortex_m7_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x00000000;
> cpu->isar.id_mmfr2 = 0x01000000;
> cpu->isar.id_mmfr3 = 0x00000000;
> - cpu->isar.id_isar0 = 0x01101110;
> - cpu->isar.id_isar1 = 0x02112000;
> - cpu->isar.id_isar2 = 0x20232231;
> - cpu->isar.id_isar3 = 0x01111131;
> - cpu->isar.id_isar4 = 0x01310132;
> - cpu->isar.id_isar5 = 0x00000000;
> - cpu->isar.id_isar6 = 0x00000000;
> + SET_IDREG(idregs, ID_ISAR0, 0x01101110);
> + SET_IDREG(idregs, ID_ISAR1, 0x02112000);
> + SET_IDREG(idregs, ID_ISAR2, 0x20232231);
> + SET_IDREG(idregs, ID_ISAR3, 0x01111131);
> + SET_IDREG(idregs, ID_ISAR4, 0x01310132);
> + SET_IDREG(idregs, ID_ISAR5, 0x00000000);
> + SET_IDREG(idregs, ID_ISAR6, 0x00000000);
> }
>
> static void cortex_m33_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + uint64_t *idregs = cpu->isar.idregs;
>
> set_feature(&cpu->env, ARM_FEATURE_V8);
> set_feature(&cpu->env, ARM_FEATURE_M);
> @@ -183,13 +188,13 @@ static void cortex_m33_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x00000000;
> cpu->isar.id_mmfr2 = 0x01000000;
> cpu->isar.id_mmfr3 = 0x00000000;
> - cpu->isar.id_isar0 = 0x01101110;
> - cpu->isar.id_isar1 = 0x02212000;
> - cpu->isar.id_isar2 = 0x20232232;
> - cpu->isar.id_isar3 = 0x01111131;
> - cpu->isar.id_isar4 = 0x01310132;
> - cpu->isar.id_isar5 = 0x00000000;
> - cpu->isar.id_isar6 = 0x00000000;
> + SET_IDREG(idregs, ID_ISAR0, 0x01101110);
> + SET_IDREG(idregs, ID_ISAR1, 0x02212000);
> + SET_IDREG(idregs, ID_ISAR2, 0x20232232);
> + SET_IDREG(idregs, ID_ISAR3, 0x01111131);
> + SET_IDREG(idregs, ID_ISAR4, 0x01310132);
> + SET_IDREG(idregs, ID_ISAR5, 0x00000000);
> + SET_IDREG(idregs, ID_ISAR6, 0x00000000);
> cpu->clidr = 0x00000000;
> cpu->ctr = 0x8000c000;
> }
> @@ -197,6 +202,7 @@ static void cortex_m33_initfn(Object *obj)
> static void cortex_m55_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + uint64_t *idregs = cpu->isar.idregs;
>
> set_feature(&cpu->env, ARM_FEATURE_V8);
> set_feature(&cpu->env, ARM_FEATURE_V8_1M);
> @@ -220,13 +226,13 @@ static void cortex_m55_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x00000000;
> cpu->isar.id_mmfr2 = 0x01000000;
> cpu->isar.id_mmfr3 = 0x00000011;
> - cpu->isar.id_isar0 = 0x01103110;
> - cpu->isar.id_isar1 = 0x02212000;
> - cpu->isar.id_isar2 = 0x20232232;
> - cpu->isar.id_isar3 = 0x01111131;
> - cpu->isar.id_isar4 = 0x01310132;
> - cpu->isar.id_isar5 = 0x00000000;
> - cpu->isar.id_isar6 = 0x00000000;
> + SET_IDREG(idregs, ID_ISAR0, 0x01103110);
> + SET_IDREG(idregs, ID_ISAR1, 0x02212000);
> + SET_IDREG(idregs, ID_ISAR2, 0x20232232);
> + SET_IDREG(idregs, ID_ISAR3, 0x01111131);
> + SET_IDREG(idregs, ID_ISAR4, 0x01310132);
> + SET_IDREG(idregs, ID_ISAR5, 0x00000000);
> + SET_IDREG(idregs, ID_ISAR6, 0x00000000);
> cpu->clidr = 0x00000000; /* caches not implemented */
> cpu->ctr = 0x8303c003;
> }
> diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
> index 2c45b7eddda7..d022ba3c9b32 100644
> --- a/target/arm/tcg/cpu32.c
> +++ b/target/arm/tcg/cpu32.c
> @@ -23,18 +23,19 @@
> void aa32_max_features(ARMCPU *cpu)
> {
> uint32_t t;
> + ARMISARegisters *isar = &cpu->isar;
>
> /* Add additional features supported by QEMU */
> - t = cpu->isar.id_isar5;
> + t = GET_IDREG(isar, ID_ISAR5);
> t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
> t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
> t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
> t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
> t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
> t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
> - cpu->isar.id_isar5 = t;
> + SET_IDREG(isar, ID_ISAR5, t);
>
> - t = cpu->isar.id_isar6;
> + t = GET_IDREG(isar, ID_ISAR6);
> t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
> t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
> t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
> @@ -42,7 +43,7 @@ void aa32_max_features(ARMCPU *cpu)
> t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
> t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
> t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
> - cpu->isar.id_isar6 = t;
> + SET_IDREG(isar, ID_ISAR6, t);
>
> t = cpu->isar.mvfr1;
> t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
> @@ -140,7 +141,7 @@ static void arm926_initfn(Object *obj)
> * ARMv5 does not have the ID_ISAR registers, but we can still
> * set the field to indicate Jazelle support within QEMU.
> */
> - cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
> + FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1);
> /*
> * Similarly, we need to set MVFR0 fields to enable vfp and short vector
> * support even though ARMv5 doesn't have this register.
> @@ -182,7 +183,7 @@ static void arm1026_initfn(Object *obj)
> * ARMv5 does not have the ID_ISAR registers, but we can still
> * set the field to indicate Jazelle support within QEMU.
> */
> - cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
> + FIELD_DP32_IDREG(&cpu->isar, ID_ISAR1, JAZELLE, 1);
> /*
> * Similarly, we need to set MVFR0 fields to enable vfp and short vector
> * support even though ARMv5 doesn't have this register.
> @@ -206,6 +207,7 @@ static void arm1026_initfn(Object *obj)
> static void arm1136_r2_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
> /*
> * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
> * older core than plain "arm1136". In particular this does not
> @@ -233,17 +235,18 @@ static void arm1136_r2_initfn(Object *obj)
> cpu->isar.id_mmfr0 = 0x01130003;
> cpu->isar.id_mmfr1 = 0x10030302;
> cpu->isar.id_mmfr2 = 0x01222110;
> - cpu->isar.id_isar0 = 0x00140011;
> - cpu->isar.id_isar1 = 0x12002111;
> - cpu->isar.id_isar2 = 0x11231111;
> - cpu->isar.id_isar3 = 0x01102131;
> - cpu->isar.id_isar4 = 0x141;
> + SET_IDREG(isar, ID_ISAR0, 0x00140011);
> + SET_IDREG(isar, ID_ISAR1, 0x12002111);
> + SET_IDREG(isar, ID_ISAR2, 0x11231111);
> + SET_IDREG(isar, ID_ISAR3, 0x01102131);
> + SET_IDREG(isar, ID_ISAR4, 0x141);
> cpu->reset_auxcr = 7;
> }
>
> static void arm1136_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,arm1136";
> set_feature(&cpu->env, ARM_FEATURE_V6K);
> @@ -264,17 +267,18 @@ static void arm1136_initfn(Object *obj)
> cpu->isar.id_mmfr0 = 0x01130003;
> cpu->isar.id_mmfr1 = 0x10030302;
> cpu->isar.id_mmfr2 = 0x01222110;
> - cpu->isar.id_isar0 = 0x00140011;
> - cpu->isar.id_isar1 = 0x12002111;
> - cpu->isar.id_isar2 = 0x11231111;
> - cpu->isar.id_isar3 = 0x01102131;
> - cpu->isar.id_isar4 = 0x141;
> + SET_IDREG(isar, ID_ISAR0, 0x00140011);
> + SET_IDREG(isar, ID_ISAR1, 0x12002111);
> + SET_IDREG(isar, ID_ISAR2, 0x11231111);
> + SET_IDREG(isar, ID_ISAR3, 0x01102131);
> + SET_IDREG(isar, ID_ISAR4, 0x141);
> cpu->reset_auxcr = 7;
> }
>
> static void arm1176_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,arm1176";
> set_feature(&cpu->env, ARM_FEATURE_V6K);
> @@ -296,17 +300,18 @@ static void arm1176_initfn(Object *obj)
> cpu->isar.id_mmfr0 = 0x01130003;
> cpu->isar.id_mmfr1 = 0x10030302;
> cpu->isar.id_mmfr2 = 0x01222100;
> - cpu->isar.id_isar0 = 0x0140011;
> - cpu->isar.id_isar1 = 0x12002111;
> - cpu->isar.id_isar2 = 0x11231121;
> - cpu->isar.id_isar3 = 0x01102131;
> - cpu->isar.id_isar4 = 0x01141;
> + SET_IDREG(isar, ID_ISAR0, 0x0140011);
> + SET_IDREG(isar, ID_ISAR1, 0x12002111);
> + SET_IDREG(isar, ID_ISAR2, 0x11231121);
> + SET_IDREG(isar, ID_ISAR3, 0x01102131);
> + SET_IDREG(isar, ID_ISAR4, 0x01141);
> cpu->reset_auxcr = 7;
> }
>
> static void arm11mpcore_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,arm11mpcore";
> set_feature(&cpu->env, ARM_FEATURE_V6K);
> @@ -325,11 +330,11 @@ static void arm11mpcore_initfn(Object *obj)
> cpu->isar.id_mmfr0 = 0x01100103;
> cpu->isar.id_mmfr1 = 0x10020302;
> cpu->isar.id_mmfr2 = 0x01222000;
> - cpu->isar.id_isar0 = 0x00100011;
> - cpu->isar.id_isar1 = 0x12002111;
> - cpu->isar.id_isar2 = 0x11221011;
> - cpu->isar.id_isar3 = 0x01102131;
> - cpu->isar.id_isar4 = 0x141;
> + SET_IDREG(isar, ID_ISAR0, 0x00100011);
> + SET_IDREG(isar, ID_ISAR1, 0x12002111);
> + SET_IDREG(isar, ID_ISAR2, 0x11221011);
> + SET_IDREG(isar, ID_ISAR3, 0x01102131);
> + SET_IDREG(isar, ID_ISAR4, 0x141);
> cpu->reset_auxcr = 1;
> }
>
> @@ -343,6 +348,7 @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
> static void cortex_a8_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,cortex-a8";
> set_feature(&cpu->env, ARM_FEATURE_V7);
> @@ -365,11 +371,11 @@ static void cortex_a8_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x20000000;
> cpu->isar.id_mmfr2 = 0x01202000;
> cpu->isar.id_mmfr3 = 0x11;
> - cpu->isar.id_isar0 = 0x00101111;
> - cpu->isar.id_isar1 = 0x12112111;
> - cpu->isar.id_isar2 = 0x21232031;
> - cpu->isar.id_isar3 = 0x11112131;
> - cpu->isar.id_isar4 = 0x00111142;
> + SET_IDREG(isar, ID_ISAR0, 0x00101111);
> + SET_IDREG(isar, ID_ISAR1, 0x12112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232031);
> + SET_IDREG(isar, ID_ISAR3, 0x11112131);
> + SET_IDREG(isar, ID_ISAR4, 0x00111142);
> cpu->isar.dbgdidr = 0x15141000;
> cpu->clidr = (1 << 27) | (2 << 24) | 3;
> cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
> @@ -412,6 +418,7 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
> static void cortex_a9_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,cortex-a9";
> set_feature(&cpu->env, ARM_FEATURE_V7);
> @@ -440,11 +447,11 @@ static void cortex_a9_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x20000000;
> cpu->isar.id_mmfr2 = 0x01230000;
> cpu->isar.id_mmfr3 = 0x00002111;
> - cpu->isar.id_isar0 = 0x00101111;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232041;
> - cpu->isar.id_isar3 = 0x11112131;
> - cpu->isar.id_isar4 = 0x00111142;
> + SET_IDREG(isar, ID_ISAR0, 0x00101111);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232041);
> + SET_IDREG(isar, ID_ISAR3, 0x11112131);
> + SET_IDREG(isar, ID_ISAR4, 0x00111142);
> cpu->isar.dbgdidr = 0x35141000;
> cpu->clidr = (1 << 27) | (1 << 24) | 3;
> cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
> @@ -479,6 +486,7 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
> static void cortex_a7_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,cortex-a7";
> set_feature(&cpu->env, ARM_FEATURE_V7VE);
> @@ -509,11 +517,11 @@ static void cortex_a7_initfn(Object *obj)
> * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
> * table 4-41 gives 0x02101110, which includes the arm div insns.
> */
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232041;
> - cpu->isar.id_isar3 = 0x11112131;
> - cpu->isar.id_isar4 = 0x10011142;
> + SET_IDREG(isar, ID_ISAR0, 0x02101110);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232041);
> + SET_IDREG(isar, ID_ISAR3, 0x11112131);
> + SET_IDREG(isar, ID_ISAR4, 0x10011142);
> cpu->isar.dbgdidr = 0x3515f005;
> cpu->isar.dbgdevid = 0x01110f13;
> cpu->isar.dbgdevid1 = 0x1;
> @@ -528,6 +536,7 @@ static void cortex_a7_initfn(Object *obj)
> static void cortex_a15_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> cpu->dtb_compatible = "arm,cortex-a15";
> set_feature(&cpu->env, ARM_FEATURE_V7VE);
> @@ -556,11 +565,11 @@ static void cortex_a15_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x20000000;
> cpu->isar.id_mmfr2 = 0x01240000;
> cpu->isar.id_mmfr3 = 0x02102211;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232041;
> - cpu->isar.id_isar3 = 0x11112131;
> - cpu->isar.id_isar4 = 0x10011142;
> + SET_IDREG(isar, ID_ISAR0, 0x02101110);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232041);
> + SET_IDREG(isar, ID_ISAR3, 0x11112131);
> + SET_IDREG(isar, ID_ISAR4, 0x10011142);
> cpu->isar.dbgdidr = 0x3515f021;
> cpu->isar.dbgdevid = 0x01110f13;
> cpu->isar.dbgdevid1 = 0x0;
> @@ -585,6 +594,7 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
> static void cortex_r5_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> set_feature(&cpu->env, ARM_FEATURE_V7);
> set_feature(&cpu->env, ARM_FEATURE_V7MP);
> @@ -599,13 +609,13 @@ static void cortex_r5_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x00000000;
> cpu->isar.id_mmfr2 = 0x01200000;
> cpu->isar.id_mmfr3 = 0x0211;
> - cpu->isar.id_isar0 = 0x02101111;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232141;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x0010142;
> - cpu->isar.id_isar5 = 0x0;
> - cpu->isar.id_isar6 = 0x0;
> + SET_IDREG(isar, ID_ISAR0, 0x02101111);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232141);
> + SET_IDREG(isar, ID_ISAR3, 0x01112131);
> + SET_IDREG(isar, ID_ISAR4, 0x0010142);
> + SET_IDREG(isar, ID_ISAR5, 0x21232141);
glurp this one is bad
it should be SET_IDREG(isar, ID_ISAR5, 0x0);
Eric
> + SET_IDREG(isar, ID_ISAR6, 0x0);
> cpu->mp_is_up = true;
> cpu->pmsav7_dregion = 16;
> cpu->isar.reset_pmcr_el0 = 0x41151800;
> @@ -720,6 +730,7 @@ static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
> static void cortex_r52_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> set_feature(&cpu->env, ARM_FEATURE_V8);
> set_feature(&cpu->env, ARM_FEATURE_EL2);
> @@ -746,12 +757,12 @@ static void cortex_r52_initfn(Object *obj)
> cpu->isar.id_mmfr2 = 0x01200000;
> cpu->isar.id_mmfr3 = 0xf0102211;
> cpu->isar.id_mmfr4 = 0x00000010;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232142;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00010142;
> - cpu->isar.id_isar5 = 0x00010001;
> + SET_IDREG(isar, ID_ISAR0, 0x02101110);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232142);
> + SET_IDREG(isar, ID_ISAR3, 0x01112131);
> + SET_IDREG(isar, ID_ISAR4, 0x00010142);
> + SET_IDREG(isar, ID_ISAR5, 0x00010001);
> cpu->isar.dbgdidr = 0x77168000;
> cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
> cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
> @@ -949,6 +960,7 @@ static void pxa270c5_initfn(Object *obj)
> static void arm_max_initfn(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> + ARMISARegisters *isar = &cpu->isar;
>
> /* aarch64_a57_initfn, advertising none of the aarch64 features */
> cpu->dtb_compatible = "arm,cortex-a57";
> @@ -976,13 +988,13 @@ static void arm_max_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x40000000;
> cpu->isar.id_mmfr2 = 0x01260000;
> cpu->isar.id_mmfr3 = 0x02102211;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00011142;
> - cpu->isar.id_isar5 = 0x00011121;
> - cpu->isar.id_isar6 = 0;
> + SET_IDREG(isar, ID_ISAR0, 0x02101110);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232042);
> + SET_IDREG(isar, ID_ISAR3, 0x01112131);
> + SET_IDREG(isar, ID_ISAR4, 0x00011142);
> + SET_IDREG(isar, ID_ISAR5, 0x00011121);
> + SET_IDREG(isar, ID_ISAR6, 0);
> cpu->isar.reset_pmcr_el0 = 0x41013000;
> cpu->clidr = 0x0a200023;
> cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index cadc1258fc40..ad47279cdd46 100644
> --- a/target/arm/tcg/cpu64.c
> +++ b/target/arm/tcg/cpu64.c
> @@ -57,12 +57,12 @@ static void aarch64_a35_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x40000000;
> cpu->isar.id_mmfr2 = 0x01260000;
> cpu->isar.id_mmfr3 = 0x02102211;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00011142;
> - cpu->isar.id_isar5 = 0x00011121;
> + SET_IDREG(isar, ID_ISAR0, 0x02101110);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232042);
> + SET_IDREG(isar, ID_ISAR3, 0x01112131);
> + SET_IDREG(isar, ID_ISAR4, 0x00011142);
> + SET_IDREG(isar, ID_ISAR5, 0x00011121);
> SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> SET_IDREG(isar, ID_AA64PFR1, 0);
> SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
> @@ -229,13 +229,13 @@ static void aarch64_a55_initfn(Object *obj)
> SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
> cpu->id_afr0 = 0x00000000;
> cpu->isar.id_dfr0 = 0x04010088;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00011142;
> - cpu->isar.id_isar5 = 0x01011121;
> - cpu->isar.id_isar6 = 0x00000010;
> + SET_IDREG(isar, ID_ISAR0, 0x02101110);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232042);
> + SET_IDREG(isar, ID_ISAR3, 0x01112131);
> + SET_IDREG(isar, ID_ISAR4, 0x00011142);
> + SET_IDREG(isar, ID_ISAR5, 0x01011121);
> + SET_IDREG(isar, ID_ISAR6, 0x00000010);
> cpu->isar.id_mmfr0 = 0x10201105;
> cpu->isar.id_mmfr1 = 0x40000000;
> cpu->isar.id_mmfr2 = 0x01260000;
> @@ -303,12 +303,12 @@ static void aarch64_a72_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x40000000;
> cpu->isar.id_mmfr2 = 0x01260000;
> cpu->isar.id_mmfr3 = 0x02102211;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00011142;
> - cpu->isar.id_isar5 = 0x00011121;
> + SET_IDREG(isar, ID_ISAR0, 0x02101110);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232042);
> + SET_IDREG(isar, ID_ISAR3, 0x01112131);
> + SET_IDREG(isar, ID_ISAR4, 0x00011142);
> + SET_IDREG(isar, ID_ISAR5, 0x00011121);
> SET_IDREG(isar, ID_AA64PFR0, 0x00002222);
> SET_IDREG(isar, ID_AA64DFR0, 0x10305106);
> SET_IDREG(isar, ID_AA64ISAR0, 0x00011120);
> @@ -362,13 +362,13 @@ static void aarch64_a76_initfn(Object *obj)
> SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
> cpu->id_afr0 = 0x00000000;
> cpu->isar.id_dfr0 = 0x04010088;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00010142;
> - cpu->isar.id_isar5 = 0x01011121;
> - cpu->isar.id_isar6 = 0x00000010;
> + SET_IDREG(isar, ID_ISAR0, 0x02101110);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232042);
> + SET_IDREG(isar, ID_ISAR3, 0x01112131);
> + SET_IDREG(isar, ID_ISAR4, 0x00010142);
> + SET_IDREG(isar, ID_ISAR5, 0x01011121);
> + SET_IDREG(isar, ID_ISAR6, 0x00000010);
> cpu->isar.id_mmfr0 = 0x10201105;
> cpu->isar.id_mmfr1 = 0x40000000;
> cpu->isar.id_mmfr2 = 0x01260000;
> @@ -610,13 +610,13 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
> SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
> cpu->id_afr0 = 0x00000000;
> cpu->isar.id_dfr0 = 0x04010088;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00010142;
> - cpu->isar.id_isar5 = 0x01011121;
> - cpu->isar.id_isar6 = 0x00000010;
> + SET_IDREG(isar, ID_ISAR0, 0x02101110);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232042);
> + SET_IDREG(isar, ID_ISAR3, 0x01112131);
> + SET_IDREG(isar, ID_ISAR4, 0x00010142);
> + SET_IDREG(isar, ID_ISAR5, 0x01011121);
> + SET_IDREG(isar, ID_ISAR6, 0x00000010);
> cpu->isar.id_mmfr0 = 0x10201105;
> cpu->isar.id_mmfr1 = 0x40000000;
> cpu->isar.id_mmfr2 = 0x01260000;
> @@ -689,13 +689,13 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
> SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
> cpu->id_afr0 = 0x00000000;
> cpu->isar.id_dfr0 = 0x15011099;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00010142;
> - cpu->isar.id_isar5 = 0x11011121;
> - cpu->isar.id_isar6 = 0x01100111;
> + SET_IDREG(isar, ID_ISAR0, 0x02101110);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232042);
> + SET_IDREG(isar, ID_ISAR3, 0x01112131);
> + SET_IDREG(isar, ID_ISAR4, 0x00010142);
> + SET_IDREG(isar, ID_ISAR5, 0x11011121);
> + SET_IDREG(isar, ID_ISAR6, 0x01100111);
> cpu->isar.id_mmfr0 = 0x10201105;
> cpu->isar.id_mmfr1 = 0x40000000;
> cpu->isar.id_mmfr2 = 0x01260000;
> @@ -910,14 +910,14 @@ static void aarch64_a710_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x40000000;
> cpu->isar.id_mmfr2 = 0x01260000;
> cpu->isar.id_mmfr3 = 0x02122211;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00010142;
> - cpu->isar.id_isar5 = 0x11011121; /* with Crypto */
> + SET_IDREG(isar, ID_ISAR0, 0x02101110);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232042);
> + SET_IDREG(isar, ID_ISAR3, 0x01112131);
> + SET_IDREG(isar, ID_ISAR4, 0x00010142);
> + SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */
> cpu->isar.id_mmfr4 = 0x21021110;
> - cpu->isar.id_isar6 = 0x01111111;
> + SET_IDREG(isar, ID_ISAR6, 0x01111111);
> cpu->isar.mvfr0 = 0x10110222;
> cpu->isar.mvfr1 = 0x13211111;
> cpu->isar.mvfr2 = 0x00000043;
> @@ -1013,14 +1013,14 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
> cpu->isar.id_mmfr1 = 0x40000000;
> cpu->isar.id_mmfr2 = 0x01260000;
> cpu->isar.id_mmfr3 = 0x02122211;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00010142;
> - cpu->isar.id_isar5 = 0x11011121; /* with Crypto */
> + SET_IDREG(isar, ID_ISAR0, 0x02101110);
> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
> + SET_IDREG(isar, ID_ISAR2, 0x21232042);
> + SET_IDREG(isar, ID_ISAR3, 0x01112131);
> + SET_IDREG(isar, ID_ISAR4, 0x00010142);
> + SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */
> cpu->isar.id_mmfr4 = 0x01021110;
> - cpu->isar.id_isar6 = 0x01111111;
> + SET_IDREG(isar, ID_ISAR6, 0x01111111);
> cpu->isar.mvfr0 = 0x10110222;
> cpu->isar.mvfr1 = 0x13211111;
> cpu->isar.mvfr2 = 0x00000043;
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH for-10.1 v5 08/13] arm/cpu: Store id_isar0-7 into the idregs array
2025-04-28 16:04 ` Eric Auger
@ 2025-04-29 9:51 ` Cornelia Huck
0 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-04-29 9:51 UTC (permalink / raw)
To: eric.auger, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini
On Mon, Apr 28 2025, Eric Auger <eric.auger@redhat.com> wrote:
> On 4/9/25 4:42 PM, Cornelia Huck wrote:
>> From: Eric Auger <eric.auger@redhat.com>
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Reviewed-by: Sebastian Ott <sebott@redhat.com>
>> Signed-off-by: Eric Auger <eric.auger@redhat.com>
>> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
>> ---
>> hw/intc/armv7m_nvic.c | 12 ++--
>> target/arm/cpu-features.h | 36 +++++-----
>> target/arm/cpu.c | 24 +++----
>> target/arm/cpu.h | 7 --
>> target/arm/cpu64.c | 28 ++++----
>> target/arm/helper.c | 14 ++--
>> target/arm/kvm.c | 21 ++----
>> target/arm/tcg/cpu-v7m.c | 90 +++++++++++++-----------
>> target/arm/tcg/cpu32.c | 144 +++++++++++++++++++++-----------------
>> target/arm/tcg/cpu64.c | 108 ++++++++++++++--------------
>> 10 files changed, 243 insertions(+), 241 deletions(-)
>> @@ -599,13 +609,13 @@ static void cortex_r5_initfn(Object *obj)
>> cpu->isar.id_mmfr1 = 0x00000000;
>> cpu->isar.id_mmfr2 = 0x01200000;
>> cpu->isar.id_mmfr3 = 0x0211;
>> - cpu->isar.id_isar0 = 0x02101111;
>> - cpu->isar.id_isar1 = 0x13112111;
>> - cpu->isar.id_isar2 = 0x21232141;
>> - cpu->isar.id_isar3 = 0x01112131;
>> - cpu->isar.id_isar4 = 0x0010142;
>> - cpu->isar.id_isar5 = 0x0;
>> - cpu->isar.id_isar6 = 0x0;
>> + SET_IDREG(isar, ID_ISAR0, 0x02101111);
>> + SET_IDREG(isar, ID_ISAR1, 0x13112111);
>> + SET_IDREG(isar, ID_ISAR2, 0x21232141);
>> + SET_IDREG(isar, ID_ISAR3, 0x01112131);
>> + SET_IDREG(isar, ID_ISAR4, 0x0010142);
>> + SET_IDREG(isar, ID_ISAR5, 0x21232141);
> glurp this one is bad
> it should be SET_IDREG(isar, ID_ISAR5, 0x0);
Huh, no idea where that came from. Fixing.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH for-10.1 v5 09/13] arm/cpu: Store id_pfr0/1/2 into the idregs array
2025-04-09 14:42 [PATCH for-10.1 v5 00/13] arm: rework id register storage Cornelia Huck
` (7 preceding siblings ...)
2025-04-09 14:42 ` [PATCH for-10.1 v5 08/13] arm/cpu: Store id_isar0-7 " Cornelia Huck
@ 2025-04-09 14:43 ` Cornelia Huck
2025-04-09 14:43 ` [PATCH for-10.1 v5 10/13] arm/cpu: Store id_dfr0/1 " Cornelia Huck
` (4 subsequent siblings)
13 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-04-09 14:43 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
hw/intc/armv7m_nvic.c | 5 +-
target/arm/cpu-features.h | 10 ++--
target/arm/cpu.c | 8 +--
target/arm/cpu.h | 3 -
target/arm/cpu64.c | 8 +--
target/arm/helper.c | 8 +--
target/arm/kvm.c | 3 +-
target/arm/tcg/cpu-v7m.c | 120 +++++++++++++++++++-------------------
target/arm/tcg/cpu32.c | 52 ++++++++---------
target/arm/tcg/cpu64.c | 44 +++++++-------
10 files changed, 128 insertions(+), 133 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 55e726be7a2c..407933eaf42e 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -988,6 +988,7 @@ static void nvic_nmi_trigger(void *opaque, int n, int level)
static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
{
ARMCPU *cpu = s->cpu;
+ ARMISARegisters *isar = &cpu->isar;
uint32_t val;
switch (offset) {
@@ -1263,12 +1264,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_pfr0;
+ return GET_IDREG(isar, ID_PFR0);
case 0xd44: /* PFR1. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_pfr1;
+ return GET_IDREG(isar, ID_PFR1);
case 0xd48: /* DFR0. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 003cf735e8ef..156130085067 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -136,12 +136,12 @@ static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
+ return FIELD_EX32_IDREG(id, ID_PFR0, RAS) != 0;
}
static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
+ return FIELD_EX32_IDREG(id, ID_PFR1, MPROGMOD) != 0;
}
static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
@@ -150,7 +150,7 @@ static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
* Return true if M-profile state handling insns
* (VSCCLRM, CLRM, FPCTX access insns) are implemented
*/
- return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
+ return FIELD_EX32_IDREG(id, ID_PFR1, SECURITY) >= 3;
}
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
@@ -349,12 +349,12 @@ static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
+ return FIELD_EX32_IDREG(id, ID_PFR0, DIT) != 0;
}
static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
+ return FIELD_EX32_IDREG(id, ID_PFR2, SSBS) != 0;
}
static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 45d922110c17..51027e279f5f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2323,7 +2323,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* Disable the security extension feature bits in the processor
* feature registers as well.
*/
- cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
+ FIELD_DP32_IDREG(isar, ID_PFR1, SECURITY, 0);
cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0);
@@ -2363,8 +2363,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* registers if we don't have EL2.
*/
FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL2, 0);
- cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
- ID_PFR1, VIRTUALIZATION, 0);
+ FIELD_DP32_IDREG(isar, ID_PFR1, VIRTUALIZATION, 0);
}
if (cpu_isar_feature(aa64_mte, cpu)) {
@@ -2427,8 +2426,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0);
/* FEAT_AMU (Activity Monitors Extension) */
FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0);
- cpu->isar.id_pfr0 =
- FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0);
+ FIELD_DP32_IDREG(isar, ID_PFR0, AMU, 0);
/* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
FIELD_DP64_IDREG(isar, ID_AA64PFR0, MPAM, 0);
}
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c98bdc1687c0..3d68938c2893 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1079,9 +1079,6 @@ struct ArchCPU {
uint32_t id_mmfr3;
uint32_t id_mmfr4;
uint32_t id_mmfr5;
- uint32_t id_pfr0;
- uint32_t id_pfr1;
- uint32_t id_pfr2;
uint32_t mvfr0;
uint32_t mvfr1;
uint32_t mvfr2;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 1489ebb1015e..a35acf63aef7 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -652,8 +652,8 @@ static void aarch64_a57_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50838;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
+ SET_IDREG(isar, ID_PFR0, 0x00000131);
+ SET_IDREG(isar, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
@@ -714,8 +714,8 @@ static void aarch64_a53_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
cpu->reset_sctlr = 0x00c50838;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
+ SET_IDREG(isar, ID_PFR0, 0x00000131);
+ SET_IDREG(isar, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1ba8551f6db8..86f21ad2a18c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6929,7 +6929,7 @@ static void define_pmu_regs(ARMCPU *cpu)
static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = env_archcpu(env);
- uint64_t pfr1 = cpu->isar.id_pfr1;
+ uint64_t pfr1 = GET_IDREG(&cpu->isar, ID_PFR1);
if (env->gicv3state) {
pfr1 |= 1 << 28;
@@ -7775,7 +7775,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_pfr0 },
+ .resetvalue = GET_IDREG(isar, ID_PFR0)},
/*
* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
* the value of the GIC field until after we define these regs.
@@ -7786,7 +7786,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.accessfn = access_aa32_tid3,
#ifdef CONFIG_USER_ONLY
.type = ARM_CP_CONST,
- .resetvalue = cpu->isar.id_pfr1,
+ .resetvalue = GET_IDREG(isar, ID_PFR1),
#else
.type = ARM_CP_NO_RAW,
.accessfn = access_aa32_tid3,
@@ -8128,7 +8128,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_pfr2 },
+ .resetvalue = GET_IDREG(isar, ID_PFR2)},
{ .name = "ID_DFR1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index ceb7e7bec7a2..91610d45aef8 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -399,8 +399,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ARM64_SYS_REG(3, 0, 0, 3, 1));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
ARM64_SYS_REG(3, 0, 0, 3, 2));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2,
- ARM64_SYS_REG(3, 0, 0, 3, 4));
+ err |= get_host_cpu_reg(fd, ahcf, ID_PFR2_EL1_IDX);
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1,
ARM64_SYS_REG(3, 0, 0, 3, 5));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5,
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index 9d5938abdb4b..aa86fdd528f4 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -45,7 +45,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
static void cortex_m0_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
- uint64_t *idregs = cpu->isar.idregs;
+ ARMISARegisters *isar = &cpu->isar;
set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_M);
@@ -59,53 +59,53 @@ static void cortex_m0_initfn(Object *obj)
* by looking at ID register fields. We use the same values as
* for the M3.
*/
- cpu->isar.id_pfr0 = 0x00000030;
- cpu->isar.id_pfr1 = 0x00000200;
+ SET_IDREG(isar, ID_PFR0, 0x00000030);
+ SET_IDREG(isar, ID_PFR1, 0x00000200);
cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x00000000;
cpu->isar.id_mmfr3 = 0x00000000;
- SET_IDREG(idregs, ID_ISAR0, 0x01141110);
- SET_IDREG(idregs, ID_ISAR1, 0x02111000);
- SET_IDREG(idregs, ID_ISAR2, 0x21112231);
- SET_IDREG(idregs, ID_ISAR3, 0x01111110);
- SET_IDREG(idregs, ID_ISAR4, 0x01310102);
- SET_IDREG(idregs, ID_ISAR5, 0x00000000);
- SET_IDREG(idregs, ID_ISAR6, 0x00000000);
+ SET_IDREG(isar, ID_ISAR0, 0x01141110);
+ SET_IDREG(isar, ID_ISAR1, 0x02111000);
+ SET_IDREG(isar, ID_ISAR2, 0x21112231);
+ SET_IDREG(isar, ID_ISAR3, 0x01111110);
+ SET_IDREG(isar, ID_ISAR4, 0x01310102);
+ SET_IDREG(isar, ID_ISAR5, 0x00000000);
+ SET_IDREG(isar, ID_ISAR6, 0x00000000);
}
static void cortex_m3_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
- uint64_t *idregs = cpu->isar.idregs;
+ ARMISARegisters *isar = &cpu->isar;
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_M);
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
cpu->midr = 0x410fc231;
cpu->pmsav7_dregion = 8;
- cpu->isar.id_pfr0 = 0x00000030;
- cpu->isar.id_pfr1 = 0x00000200;
+ SET_IDREG(isar, ID_PFR0, 0x00000030);
+ SET_IDREG(isar, ID_PFR1, 0x00000200);
cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x00000000;
cpu->isar.id_mmfr3 = 0x00000000;
- SET_IDREG(idregs, ID_ISAR0, 0x01141110);
- SET_IDREG(idregs, ID_ISAR1, 0x02111000);
- SET_IDREG(idregs, ID_ISAR2, 0x21112231);
- SET_IDREG(idregs, ID_ISAR3, 0x01111110);
- SET_IDREG(idregs, ID_ISAR4, 0x01310102);
- SET_IDREG(idregs, ID_ISAR5, 0x00000000);
- SET_IDREG(idregs, ID_ISAR6, 0x00000000);
+ SET_IDREG(isar, ID_ISAR0, 0x01141110);
+ SET_IDREG(isar, ID_ISAR1, 0x02111000);
+ SET_IDREG(isar, ID_ISAR2, 0x21112231);
+ SET_IDREG(isar, ID_ISAR3, 0x01111110);
+ SET_IDREG(isar, ID_ISAR4, 0x01310102);
+ SET_IDREG(isar, ID_ISAR5, 0x00000000);
+ SET_IDREG(isar, ID_ISAR6, 0x00000000);
}
static void cortex_m4_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
- uint64_t *idregs = cpu->isar.idregs;
+ ARMISARegisters *isar = &cpu->isar;
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_M);
@@ -116,27 +116,27 @@ static void cortex_m4_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110021;
cpu->isar.mvfr1 = 0x11000011;
cpu->isar.mvfr2 = 0x00000000;
- cpu->isar.id_pfr0 = 0x00000030;
- cpu->isar.id_pfr1 = 0x00000200;
+ SET_IDREG(isar, ID_PFR0, 0x00000030);
+ SET_IDREG(isar, ID_PFR1, 0x00000200);
cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x00000000;
cpu->isar.id_mmfr3 = 0x00000000;
- SET_IDREG(idregs, ID_ISAR0, 0x01141110);
- SET_IDREG(idregs, ID_ISAR1, 0x02111000);
- SET_IDREG(idregs, ID_ISAR2, 0x21112231);
- SET_IDREG(idregs, ID_ISAR3, 0x01111110);
- SET_IDREG(idregs, ID_ISAR4, 0x01310102);
- SET_IDREG(idregs, ID_ISAR5, 0x00000000);
- SET_IDREG(idregs, ID_ISAR6, 0x00000000);
+ SET_IDREG(isar, ID_ISAR0, 0x01141110);
+ SET_IDREG(isar, ID_ISAR1, 0x02111000);
+ SET_IDREG(isar, ID_ISAR2, 0x21112231);
+ SET_IDREG(isar, ID_ISAR3, 0x01111110);
+ SET_IDREG(isar, ID_ISAR4, 0x01310102);
+ SET_IDREG(isar, ID_ISAR5, 0x00000000);
+ SET_IDREG(isar, ID_ISAR6, 0x00000000);
}
static void cortex_m7_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
- uint64_t *idregs = cpu->isar.idregs;
+ ARMISARegisters *isar = &cpu->isar;
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_M);
@@ -147,27 +147,27 @@ static void cortex_m7_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110221;
cpu->isar.mvfr1 = 0x12000011;
cpu->isar.mvfr2 = 0x00000040;
- cpu->isar.id_pfr0 = 0x00000030;
- cpu->isar.id_pfr1 = 0x00000200;
+ SET_IDREG(isar, ID_PFR0, 0x00000030);
+ SET_IDREG(isar, ID_PFR1, 0x00000200);
cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00100030;
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x01000000;
cpu->isar.id_mmfr3 = 0x00000000;
- SET_IDREG(idregs, ID_ISAR0, 0x01101110);
- SET_IDREG(idregs, ID_ISAR1, 0x02112000);
- SET_IDREG(idregs, ID_ISAR2, 0x20232231);
- SET_IDREG(idregs, ID_ISAR3, 0x01111131);
- SET_IDREG(idregs, ID_ISAR4, 0x01310132);
- SET_IDREG(idregs, ID_ISAR5, 0x00000000);
- SET_IDREG(idregs, ID_ISAR6, 0x00000000);
+ SET_IDREG(isar, ID_ISAR0, 0x01101110);
+ SET_IDREG(isar, ID_ISAR1, 0x02112000);
+ SET_IDREG(isar, ID_ISAR2, 0x20232231);
+ SET_IDREG(isar, ID_ISAR3, 0x01111131);
+ SET_IDREG(isar, ID_ISAR4, 0x01310132);
+ SET_IDREG(isar, ID_ISAR5, 0x00000000);
+ SET_IDREG(isar, ID_ISAR6, 0x00000000);
}
static void cortex_m33_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
- uint64_t *idregs = cpu->isar.idregs;
+ ARMISARegisters *isar = &cpu->isar;
set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_M);
@@ -180,21 +180,21 @@ static void cortex_m33_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110021;
cpu->isar.mvfr1 = 0x11000011;
cpu->isar.mvfr2 = 0x00000040;
- cpu->isar.id_pfr0 = 0x00000030;
- cpu->isar.id_pfr1 = 0x00000210;
+ SET_IDREG(isar, ID_PFR0, 0x00000030);
+ SET_IDREG(isar, ID_PFR1, 0x00000210);
cpu->isar.id_dfr0 = 0x00200000;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00101F40;
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x01000000;
cpu->isar.id_mmfr3 = 0x00000000;
- SET_IDREG(idregs, ID_ISAR0, 0x01101110);
- SET_IDREG(idregs, ID_ISAR1, 0x02212000);
- SET_IDREG(idregs, ID_ISAR2, 0x20232232);
- SET_IDREG(idregs, ID_ISAR3, 0x01111131);
- SET_IDREG(idregs, ID_ISAR4, 0x01310132);
- SET_IDREG(idregs, ID_ISAR5, 0x00000000);
- SET_IDREG(idregs, ID_ISAR6, 0x00000000);
+ SET_IDREG(isar, ID_ISAR0, 0x01101110);
+ SET_IDREG(isar, ID_ISAR1, 0x02212000);
+ SET_IDREG(isar, ID_ISAR2, 0x20232232);
+ SET_IDREG(isar, ID_ISAR3, 0x01111131);
+ SET_IDREG(isar, ID_ISAR4, 0x01310132);
+ SET_IDREG(isar, ID_ISAR5, 0x00000000);
+ SET_IDREG(isar, ID_ISAR6, 0x00000000);
cpu->clidr = 0x00000000;
cpu->ctr = 0x8000c000;
}
@@ -202,7 +202,7 @@ static void cortex_m33_initfn(Object *obj)
static void cortex_m55_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
- uint64_t *idregs = cpu->isar.idregs;
+ ARMISARegisters *isar = &cpu->isar;
set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_V8_1M);
@@ -218,21 +218,21 @@ static void cortex_m55_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110221;
cpu->isar.mvfr1 = 0x12100211;
cpu->isar.mvfr2 = 0x00000040;
- cpu->isar.id_pfr0 = 0x20000030;
- cpu->isar.id_pfr1 = 0x00000230;
+ SET_IDREG(isar, ID_PFR0, 0x20000030);
+ SET_IDREG(isar, ID_PFR1, 0x00000230);
cpu->isar.id_dfr0 = 0x10200000;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00111040;
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x01000000;
cpu->isar.id_mmfr3 = 0x00000011;
- SET_IDREG(idregs, ID_ISAR0, 0x01103110);
- SET_IDREG(idregs, ID_ISAR1, 0x02212000);
- SET_IDREG(idregs, ID_ISAR2, 0x20232232);
- SET_IDREG(idregs, ID_ISAR3, 0x01111131);
- SET_IDREG(idregs, ID_ISAR4, 0x01310132);
- SET_IDREG(idregs, ID_ISAR5, 0x00000000);
- SET_IDREG(idregs, ID_ISAR6, 0x00000000);
+ SET_IDREG(isar, ID_ISAR0, 0x01103110);
+ SET_IDREG(isar, ID_ISAR1, 0x02212000);
+ SET_IDREG(isar, ID_ISAR2, 0x20232232);
+ SET_IDREG(isar, ID_ISAR3, 0x01111131);
+ SET_IDREG(isar, ID_ISAR4, 0x01310132);
+ SET_IDREG(isar, ID_ISAR5, 0x00000000);
+ SET_IDREG(isar, ID_ISAR6, 0x00000000);
cpu->clidr = 0x00000000; /* caches not implemented */
cpu->ctr = 0x8303c003;
}
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index d022ba3c9b32..dcc3064ebb86 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -71,16 +71,16 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
cpu->isar.id_mmfr5 = t;
- t = cpu->isar.id_pfr0;
+ t = GET_IDREG(isar, ID_PFR0);
t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
- cpu->isar.id_pfr0 = t;
+ SET_IDREG(isar, ID_PFR0, t);
- t = cpu->isar.id_pfr2;
+ t = GET_IDREG(isar, ID_PFR2);
t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
- cpu->isar.id_pfr2 = t;
+ SET_IDREG(isar, ID_PFR2, t);
t = cpu->isar.id_dfr0;
t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
@@ -228,8 +228,8 @@ static void arm1136_r2_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00050078;
- cpu->isar.id_pfr0 = 0x111;
- cpu->isar.id_pfr1 = 0x1;
+ SET_IDREG(isar, ID_PFR0, 0x111);
+ SET_IDREG(isar, ID_PFR1, 0x1);
cpu->isar.id_dfr0 = 0x2;
cpu->id_afr0 = 0x3;
cpu->isar.id_mmfr0 = 0x01130003;
@@ -260,8 +260,8 @@ static void arm1136_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00050078;
- cpu->isar.id_pfr0 = 0x111;
- cpu->isar.id_pfr1 = 0x1;
+ SET_IDREG(isar, ID_PFR0, 0x111);
+ SET_IDREG(isar, ID_PFR1, 0x1);
cpu->isar.id_dfr0 = 0x2;
cpu->id_afr0 = 0x3;
cpu->isar.id_mmfr0 = 0x01130003;
@@ -293,8 +293,8 @@ static void arm1176_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00050078;
- cpu->isar.id_pfr0 = 0x111;
- cpu->isar.id_pfr1 = 0x11;
+ SET_IDREG(isar, ID_PFR0, 0x111);
+ SET_IDREG(isar, ID_PFR1, 0x11);
cpu->isar.id_dfr0 = 0x33;
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x01130003;
@@ -323,8 +323,8 @@ static void arm11mpcore_initfn(Object *obj)
cpu->isar.mvfr0 = 0x11111111;
cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
- cpu->isar.id_pfr0 = 0x111;
- cpu->isar.id_pfr1 = 0x1;
+ SET_IDREG(isar, ID_PFR0, 0x111);
+ SET_IDREG(isar, ID_PFR1, 0x1);
cpu->isar.id_dfr0 = 0;
cpu->id_afr0 = 0x2;
cpu->isar.id_mmfr0 = 0x01100103;
@@ -363,8 +363,8 @@ static void cortex_a8_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00011111;
cpu->ctr = 0x82048004;
cpu->reset_sctlr = 0x00c50078;
- cpu->isar.id_pfr0 = 0x1031;
- cpu->isar.id_pfr1 = 0x11;
+ SET_IDREG(isar, ID_PFR0, 0x1031);
+ SET_IDREG(isar, ID_PFR1, 0x11);
cpu->isar.id_dfr0 = 0x400;
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x31100003;
@@ -439,8 +439,8 @@ static void cortex_a9_initfn(Object *obj)
cpu->isar.mvfr1 = 0x01111111;
cpu->ctr = 0x80038003;
cpu->reset_sctlr = 0x00c50078;
- cpu->isar.id_pfr0 = 0x1031;
- cpu->isar.id_pfr1 = 0x11;
+ SET_IDREG(isar, ID_PFR0, 0x1031);
+ SET_IDREG(isar, ID_PFR1, 0x11);
cpu->isar.id_dfr0 = 0x000;
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x00100103;
@@ -505,8 +505,8 @@ static void cortex_a7_initfn(Object *obj)
cpu->isar.mvfr1 = 0x11111111;
cpu->ctr = 0x84448003;
cpu->reset_sctlr = 0x00c50078;
- cpu->isar.id_pfr0 = 0x00001131;
- cpu->isar.id_pfr1 = 0x00011011;
+ SET_IDREG(isar, ID_PFR0, 0x00001131);
+ SET_IDREG(isar, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x02010555;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
@@ -557,8 +557,8 @@ static void cortex_a15_initfn(Object *obj)
cpu->isar.mvfr1 = 0x11111111;
cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50078;
- cpu->isar.id_pfr0 = 0x00001131;
- cpu->isar.id_pfr1 = 0x00011011;
+ SET_IDREG(isar, ID_PFR0, 0x00001131);
+ SET_IDREG(isar, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x02010555;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10201105;
@@ -601,8 +601,8 @@ static void cortex_r5_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_PMSA);
set_feature(&cpu->env, ARM_FEATURE_PMU);
cpu->midr = 0x411fc153; /* r1p3 */
- cpu->isar.id_pfr0 = 0x0131;
- cpu->isar.id_pfr1 = 0x001;
+ SET_IDREG(isar, ID_PFR0, 0x0131);
+ SET_IDREG(isar, ID_PFR1, 0x001);
cpu->isar.id_dfr0 = 0x010400;
cpu->id_afr0 = 0x0;
cpu->isar.id_mmfr0 = 0x0210030;
@@ -748,8 +748,8 @@ static void cortex_r52_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x8144c004;
cpu->reset_sctlr = 0x30c50838;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x10111001;
+ SET_IDREG(isar, ID_PFR0, 0x00000131);
+ SET_IDREG(isar, ID_PFR1, 0x10111001);
cpu->isar.id_dfr0 = 0x03010006;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00211040;
@@ -980,8 +980,8 @@ static void arm_max_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50838;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
+ SET_IDREG(isar, ID_PFR0, 0x00000131);
+ SET_IDREG(isar, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index ad47279cdd46..cfaf01fbf9bc 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -49,8 +49,8 @@ static void aarch64_a35_initfn(Object *obj)
cpu->midr = 0x411fd040;
cpu->revidr = 0;
cpu->ctr = 0x84448004;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
+ SET_IDREG(isar, ID_PFR0, 0x00000131);
+ SET_IDREG(isar, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105;
@@ -241,9 +241,9 @@ static void aarch64_a55_initfn(Object *obj)
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211;
cpu->isar.id_mmfr4 = 0x00021110;
- cpu->isar.id_pfr0 = 0x10010131;
- cpu->isar.id_pfr1 = 0x00011011;
- cpu->isar.id_pfr2 = 0x00000011;
+ SET_IDREG(isar, ID_PFR0, 0x10010131);
+ SET_IDREG(isar, ID_PFR1, 0x00011011);
+ SET_IDREG(isar, ID_PFR2, 0x00000011);
cpu->midr = 0x412FD050; /* r2p0 */
cpu->revidr = 0;
@@ -295,8 +295,8 @@ static void aarch64_a72_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50838;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
+ SET_IDREG(isar, ID_PFR0, 0x00000131);
+ SET_IDREG(isar, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10201105;
@@ -374,9 +374,9 @@ static void aarch64_a76_initfn(Object *obj)
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211;
cpu->isar.id_mmfr4 = 0x00021110;
- cpu->isar.id_pfr0 = 0x10010131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
- cpu->isar.id_pfr2 = 0x00000011;
+ SET_IDREG(isar, ID_PFR0, 0x10010131);
+ SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
+ SET_IDREG(isar, ID_PFR2, 0x00000011);
cpu->midr = 0x414fd0b1; /* r4p1 */
cpu->revidr = 0;
@@ -622,9 +622,9 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211;
cpu->isar.id_mmfr4 = 0x00021110;
- cpu->isar.id_pfr0 = 0x10010131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
- cpu->isar.id_pfr2 = 0x00000011;
+ SET_IDREG(isar, ID_PFR0, 0x10010131);
+ SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
+ SET_IDREG(isar, ID_PFR2, 0x00000011);
cpu->midr = 0x414fd0c1; /* r4p1 */
cpu->revidr = 0;
@@ -701,9 +701,9 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211;
cpu->isar.id_mmfr4 = 0x01021110;
- cpu->isar.id_pfr0 = 0x21110131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
- cpu->isar.id_pfr2 = 0x00000011;
+ SET_IDREG(isar, ID_PFR0, 0x21110131);
+ SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
+ SET_IDREG(isar, ID_PFR2, 0x00000011);
cpu->midr = 0x411FD402; /* r1p2 */
cpu->revidr = 0;
@@ -902,8 +902,8 @@ static void aarch64_a710_initfn(Object *obj)
/* Ordered by Section B.4: AArch64 registers */
cpu->midr = 0x412FD471; /* r2p1 */
cpu->revidr = 0;
- cpu->isar.id_pfr0 = 0x21110131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
+ SET_IDREG(isar, ID_PFR0, 0x21110131);
+ SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
cpu->isar.id_dfr0 = 0x16011099;
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105;
@@ -921,7 +921,7 @@ static void aarch64_a710_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043;
- cpu->isar.id_pfr2 = 0x00000011;
+ SET_IDREG(isar, ID_PFR2, 0x00000011);
SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull);
SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
@@ -1005,8 +1005,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
/* Ordered by Section B.5: AArch64 ID registers */
cpu->midr = 0x410FD493; /* r0p3 */
cpu->revidr = 0;
- cpu->isar.id_pfr0 = 0x21110131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
+ SET_IDREG(isar, ID_PFR0, 0x21110131);
+ SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
cpu->isar.id_dfr0 = 0x16011099;
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105;
@@ -1024,7 +1024,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043;
- cpu->isar.id_pfr2 = 0x00000011;
+ SET_IDREG(isar, ID_PFR2, 0x00000011);
SET_IDREG(isar, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000221ull);
SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH for-10.1 v5 10/13] arm/cpu: Store id_dfr0/1 into the idregs array
2025-04-09 14:42 [PATCH for-10.1 v5 00/13] arm: rework id register storage Cornelia Huck
` (8 preceding siblings ...)
2025-04-09 14:43 ` [PATCH for-10.1 v5 09/13] arm/cpu: Store id_pfr0/1/2 " Cornelia Huck
@ 2025-04-09 14:43 ` Cornelia Huck
2025-04-09 14:43 ` [PATCH for-10.1 v5 11/13] arm/cpu: Store id_mmfr0-5 " Cornelia Huck
` (3 subsequent siblings)
13 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-04-09 14:43 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
hw/intc/armv7m_nvic.c | 2 +-
target/arm/cpu-features.h | 16 ++++++++--------
target/arm/cpu.c | 13 +++++--------
target/arm/cpu.h | 2 --
target/arm/cpu64.c | 4 ++--
target/arm/helper.c | 4 ++--
target/arm/kvm.c | 6 ++----
target/arm/tcg/cpu-v7m.c | 12 ++++++------
target/arm/tcg/cpu32.c | 30 ++++++++++++++----------------
target/arm/tcg/cpu64.c | 16 ++++++++--------
10 files changed, 48 insertions(+), 57 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 407933eaf42e..7f42803fef7c 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1274,7 +1274,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_dfr0;
+ return GET_IDREG(isar, ID_DFR0);
case 0xd4c: /* AFR0. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 156130085067..cad34f0ad403 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -299,22 +299,22 @@ static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id)
{
/* 0xf means "non-standard IMPDEF PMU" */
- return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
- FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
+ return FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) >= 4 &&
+ FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) != 0xf;
}
static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id)
{
/* 0xf means "non-standard IMPDEF PMU" */
- return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
- FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
+ return FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) >= 5 &&
+ FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) != 0xf;
}
static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id)
{
/* 0xf means "non-standard IMPDEF PMU" */
- return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 &&
- FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
+ return FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) >= 6 &&
+ FIELD_EX32_IDREG(id, ID_DFR0, PERFMON) != 0xf;
}
static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
@@ -359,12 +359,12 @@ static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5;
+ return FIELD_EX32_IDREG(id, ID_DFR0, COPDBG) >= 5;
}
static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
+ return FIELD_EX32_IDREG(id, ID_DFR0, COPDBG) >= 8;
}
static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 51027e279f5f..a3de5ee2b19c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2324,7 +2324,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* feature registers as well.
*/
FIELD_DP32_IDREG(isar, ID_PFR1, SECURITY, 0);
- cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
+ FIELD_DP32_IDREG(isar, ID_DFR0, COPSDBG, 0);
FIELD_DP64_IDREG(isar, ID_AA64PFR0, EL3, 0);
/* Disable the realm management extension, which requires EL3. */
@@ -2352,7 +2352,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
#endif
} else {
FIELD_DP64_IDREG(isar, ID_AA64DFR0, PMUVER, 0);
- cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
+ FIELD_DP32_IDREG(isar, ID_DFR0, PERFMON, 0);
cpu->pmceid0 = 0;
cpu->pmceid1 = 0;
}
@@ -2415,15 +2415,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEBUFFER, 0);
/* FEAT_TRF (Self-hosted Trace Extension) */
FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEFILT, 0);
- cpu->isar.id_dfr0 =
- FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0);
+ FIELD_DP32_IDREG(isar, ID_DFR0, TRACEFILT, 0);
/* Trace Macrocell system register access */
FIELD_DP64_IDREG(isar, ID_AA64DFR0, TRACEVER, 0);
- cpu->isar.id_dfr0 =
- FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0);
+ FIELD_DP32_IDREG(isar, ID_DFR0, COPTRC, 0);
/* Memory mapped trace */
- cpu->isar.id_dfr0 =
- FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0);
+ FIELD_DP32_IDREG(isar, ID_DFR0, MMAPTRC, 0);
/* FEAT_AMU (Activity Monitors Extension) */
FIELD_DP64_IDREG(isar, ID_AA64PFR0, AMU, 0);
FIELD_DP32_IDREG(isar, ID_PFR0, AMU, 0);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 3d68938c2893..496c7f9a3ce7 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1082,8 +1082,6 @@ struct ArchCPU {
uint32_t mvfr0;
uint32_t mvfr1;
uint32_t mvfr2;
- uint32_t id_dfr0;
- uint32_t id_dfr1;
uint32_t dbgdidr;
uint32_t dbgdevid;
uint32_t dbgdevid1;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index a35acf63aef7..292d09fb8e9b 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -654,7 +654,7 @@ static void aarch64_a57_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50838;
SET_IDREG(isar, ID_PFR0, 0x00000131);
SET_IDREG(isar, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x03010066;
+ SET_IDREG(isar, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -716,7 +716,7 @@ static void aarch64_a53_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50838;
SET_IDREG(isar, ID_PFR0, 0x00000131);
SET_IDREG(isar, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x03010066;
+ SET_IDREG(isar, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
cpu->isar.id_mmfr1 = 0x40000000;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 86f21ad2a18c..69e9e681d21d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7798,7 +7798,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_dfr0 },
+ .resetvalue = GET_IDREG(isar, ID_DFR0)},
{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
@@ -8133,7 +8133,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_dfr1 },
+ .resetvalue = GET_IDREG(isar, ID_DFR1)},
{ .name = "ID_MMFR5", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 91610d45aef8..1f7b8d40f002 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -373,8 +373,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
*/
err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR0_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX);
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
- ARM64_SYS_REG(3, 0, 0, 1, 2));
+ err |= get_host_cpu_reg(fd, ahcf, ID_DFR0_EL1_IDX);
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
ARM64_SYS_REG(3, 0, 0, 1, 4));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
@@ -400,8 +399,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
ARM64_SYS_REG(3, 0, 0, 3, 2));
err |= get_host_cpu_reg(fd, ahcf, ID_PFR2_EL1_IDX);
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1,
- ARM64_SYS_REG(3, 0, 0, 3, 5));
+ err |= get_host_cpu_reg(fd, ahcf, ID_DFR1_EL1_IDX);
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5,
ARM64_SYS_REG(3, 0, 0, 3, 6));
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index aa86fdd528f4..eb4e9653bfb6 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -61,7 +61,7 @@ static void cortex_m0_initfn(Object *obj)
*/
SET_IDREG(isar, ID_PFR0, 0x00000030);
SET_IDREG(isar, ID_PFR1, 0x00000200);
- cpu->isar.id_dfr0 = 0x00100000;
+ SET_IDREG(isar, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -87,7 +87,7 @@ static void cortex_m3_initfn(Object *obj)
cpu->pmsav7_dregion = 8;
SET_IDREG(isar, ID_PFR0, 0x00000030);
SET_IDREG(isar, ID_PFR1, 0x00000200);
- cpu->isar.id_dfr0 = 0x00100000;
+ SET_IDREG(isar, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -118,7 +118,7 @@ static void cortex_m4_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000000;
SET_IDREG(isar, ID_PFR0, 0x00000030);
SET_IDREG(isar, ID_PFR1, 0x00000200);
- cpu->isar.id_dfr0 = 0x00100000;
+ SET_IDREG(isar, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -149,7 +149,7 @@ static void cortex_m7_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000040;
SET_IDREG(isar, ID_PFR0, 0x00000030);
SET_IDREG(isar, ID_PFR1, 0x00000200);
- cpu->isar.id_dfr0 = 0x00100000;
+ SET_IDREG(isar, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00100030;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -182,7 +182,7 @@ static void cortex_m33_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000040;
SET_IDREG(isar, ID_PFR0, 0x00000030);
SET_IDREG(isar, ID_PFR1, 0x00000210);
- cpu->isar.id_dfr0 = 0x00200000;
+ SET_IDREG(isar, ID_DFR0, 0x00200000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00101F40;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -220,7 +220,7 @@ static void cortex_m55_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000040;
SET_IDREG(isar, ID_PFR0, 0x20000030);
SET_IDREG(isar, ID_PFR1, 0x00000230);
- cpu->isar.id_dfr0 = 0x10200000;
+ SET_IDREG(isar, ID_DFR0, 0x10200000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00111040;
cpu->isar.id_mmfr1 = 0x00000000;
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index dcc3064ebb86..191b602c8c65 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -82,11 +82,11 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
SET_IDREG(isar, ID_PFR2, t);
- t = cpu->isar.id_dfr0;
+ t = GET_IDREG(isar, ID_DFR0);
t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */
t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
- cpu->isar.id_dfr0 = t;
+ SET_IDREG(isar, ID_DFR0, t);
/* Debug ID registers. */
@@ -116,9 +116,7 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
cpu->isar.dbgdevid1 = t;
- t = cpu->isar.id_dfr1;
- t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
- cpu->isar.id_dfr1 = t;
+ FIELD_DP32_IDREG(isar, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
}
/* CPU models. These are not needed for the AArch64 linux-user build. */
@@ -230,7 +228,7 @@ static void arm1136_r2_initfn(Object *obj)
cpu->reset_sctlr = 0x00050078;
SET_IDREG(isar, ID_PFR0, 0x111);
SET_IDREG(isar, ID_PFR1, 0x1);
- cpu->isar.id_dfr0 = 0x2;
+ SET_IDREG(isar, ID_DFR0, 0x2);
cpu->id_afr0 = 0x3;
cpu->isar.id_mmfr0 = 0x01130003;
cpu->isar.id_mmfr1 = 0x10030302;
@@ -262,7 +260,7 @@ static void arm1136_initfn(Object *obj)
cpu->reset_sctlr = 0x00050078;
SET_IDREG(isar, ID_PFR0, 0x111);
SET_IDREG(isar, ID_PFR1, 0x1);
- cpu->isar.id_dfr0 = 0x2;
+ SET_IDREG(isar, ID_DFR0, 0x2);
cpu->id_afr0 = 0x3;
cpu->isar.id_mmfr0 = 0x01130003;
cpu->isar.id_mmfr1 = 0x10030302;
@@ -295,7 +293,7 @@ static void arm1176_initfn(Object *obj)
cpu->reset_sctlr = 0x00050078;
SET_IDREG(isar, ID_PFR0, 0x111);
SET_IDREG(isar, ID_PFR1, 0x11);
- cpu->isar.id_dfr0 = 0x33;
+ SET_IDREG(isar, ID_DFR0, 0x33);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x01130003;
cpu->isar.id_mmfr1 = 0x10030302;
@@ -325,7 +323,7 @@ static void arm11mpcore_initfn(Object *obj)
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
SET_IDREG(isar, ID_PFR0, 0x111);
SET_IDREG(isar, ID_PFR1, 0x1);
- cpu->isar.id_dfr0 = 0;
+ SET_IDREG(isar, ID_DFR0, 0);
cpu->id_afr0 = 0x2;
cpu->isar.id_mmfr0 = 0x01100103;
cpu->isar.id_mmfr1 = 0x10020302;
@@ -365,7 +363,7 @@ static void cortex_a8_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
SET_IDREG(isar, ID_PFR0, 0x1031);
SET_IDREG(isar, ID_PFR1, 0x11);
- cpu->isar.id_dfr0 = 0x400;
+ SET_IDREG(isar, ID_DFR0, 0x400);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x31100003;
cpu->isar.id_mmfr1 = 0x20000000;
@@ -441,7 +439,7 @@ static void cortex_a9_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
SET_IDREG(isar, ID_PFR0, 0x1031);
SET_IDREG(isar, ID_PFR1, 0x11);
- cpu->isar.id_dfr0 = 0x000;
+ SET_IDREG(isar, ID_DFR0, 0x000);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x00100103;
cpu->isar.id_mmfr1 = 0x20000000;
@@ -507,7 +505,7 @@ static void cortex_a7_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
SET_IDREG(isar, ID_PFR0, 0x00001131);
SET_IDREG(isar, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x02010555;
+ SET_IDREG(isar, ID_DFR0, 0x02010555);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -559,7 +557,7 @@ static void cortex_a15_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
SET_IDREG(isar, ID_PFR0, 0x00001131);
SET_IDREG(isar, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x02010555;
+ SET_IDREG(isar, ID_DFR0, 0x02010555);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x20000000;
@@ -603,7 +601,7 @@ static void cortex_r5_initfn(Object *obj)
cpu->midr = 0x411fc153; /* r1p3 */
SET_IDREG(isar, ID_PFR0, 0x0131);
SET_IDREG(isar, ID_PFR1, 0x001);
- cpu->isar.id_dfr0 = 0x010400;
+ SET_IDREG(isar, ID_DFR0, 0x010400);
cpu->id_afr0 = 0x0;
cpu->isar.id_mmfr0 = 0x0210030;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -750,7 +748,7 @@ static void cortex_r52_initfn(Object *obj)
cpu->reset_sctlr = 0x30c50838;
SET_IDREG(isar, ID_PFR0, 0x00000131);
SET_IDREG(isar, ID_PFR1, 0x10111001);
- cpu->isar.id_dfr0 = 0x03010006;
+ SET_IDREG(isar, ID_DFR0, 0x03010006);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00211040;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -982,7 +980,7 @@ static void arm_max_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50838;
SET_IDREG(isar, ID_PFR0, 0x00000131);
SET_IDREG(isar, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x03010066;
+ SET_IDREG(isar, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
cpu->isar.id_mmfr1 = 0x40000000;
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index cfaf01fbf9bc..738826a7bf97 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -51,7 +51,7 @@ static void aarch64_a35_initfn(Object *obj)
cpu->ctr = 0x84448004;
SET_IDREG(isar, ID_PFR0, 0x00000131);
SET_IDREG(isar, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x03010066;
+ SET_IDREG(isar, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -228,7 +228,7 @@ static void aarch64_a55_initfn(Object *obj)
SET_IDREG(isar, ID_AA64PFR0, 0x0000000010112222ull);
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
+ SET_IDREG(isar, ID_DFR0, 0x04010088);
SET_IDREG(isar, ID_ISAR0, 0x02101110);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232042);
@@ -297,7 +297,7 @@ static void aarch64_a72_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50838;
SET_IDREG(isar, ID_PFR0, 0x00000131);
SET_IDREG(isar, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x03010066;
+ SET_IDREG(isar, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -361,7 +361,7 @@ static void aarch64_a76_initfn(Object *obj)
SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
+ SET_IDREG(isar, ID_DFR0, 0x04010088);
SET_IDREG(isar, ID_ISAR0, 0x02101110);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232042);
@@ -609,7 +609,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
+ SET_IDREG(isar, ID_DFR0, 0x04010088);
SET_IDREG(isar, ID_ISAR0, 0x02101110);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232042);
@@ -688,7 +688,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in later */
SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x15011099;
+ SET_IDREG(isar, ID_DFR0, 0x15011099);
SET_IDREG(isar, ID_ISAR0, 0x02101110);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232042);
@@ -904,7 +904,7 @@ static void aarch64_a710_initfn(Object *obj)
cpu->revidr = 0;
SET_IDREG(isar, ID_PFR0, 0x21110131);
SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
- cpu->isar.id_dfr0 = 0x16011099;
+ SET_IDREG(isar, ID_DFR0, 0x16011099);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -1007,7 +1007,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->revidr = 0;
SET_IDREG(isar, ID_PFR0, 0x21110131);
SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
- cpu->isar.id_dfr0 = 0x16011099;
+ SET_IDREG(isar, ID_DFR0, 0x16011099);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH for-10.1 v5 11/13] arm/cpu: Store id_mmfr0-5 into the idregs array
2025-04-09 14:42 [PATCH for-10.1 v5 00/13] arm: rework id register storage Cornelia Huck
` (9 preceding siblings ...)
2025-04-09 14:43 ` [PATCH for-10.1 v5 10/13] arm/cpu: Store id_dfr0/1 " Cornelia Huck
@ 2025-04-09 14:43 ` Cornelia Huck
2025-04-09 14:43 ` [PATCH for-10.1 v5 12/13] arm/cpu: Add sysreg generation scripts Cornelia Huck
` (2 subsequent siblings)
13 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-04-09 14:43 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
hw/intc/armv7m_nvic.c | 8 ++--
target/arm/cpu-features.h | 18 ++++----
target/arm/cpu.h | 6 ---
target/arm/cpu64.c | 16 +++----
target/arm/helper.c | 12 ++---
target/arm/kvm.c | 18 +++-----
target/arm/tcg/cpu-v7m.c | 48 ++++++++++----------
target/arm/tcg/cpu32.c | 94 +++++++++++++++++++--------------------
target/arm/tcg/cpu64.c | 76 +++++++++++++++----------------
9 files changed, 140 insertions(+), 156 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 7f42803fef7c..f6d945c52923 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1284,22 +1284,22 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_mmfr0;
+ return GET_IDREG(isar, ID_MMFR0);
case 0xd54: /* MMFR1. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_mmfr1;
+ return GET_IDREG(isar, ID_MMFR1);
case 0xd58: /* MMFR2. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_mmfr2;
+ return GET_IDREG(isar, ID_MMFR2);
case 0xd5c: /* MMFR3. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_mmfr3;
+ return GET_IDREG(isar, ID_MMFR3);
case 0xd60: /* ISAR0. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index cad34f0ad403..db3c99e42964 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -283,17 +283,17 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
+ return FIELD_EX32_IDREG(id, ID_MMFR0, VMSA) >= 4;
}
static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
+ return FIELD_EX32_IDREG(id, ID_MMFR3, PAN) != 0;
}
static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
+ return FIELD_EX32_IDREG(id, ID_MMFR3, PAN) >= 2;
}
static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id)
@@ -319,32 +319,32 @@ static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id)
static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
+ return FIELD_EX32_IDREG(id, ID_MMFR4, HPDS) != 0;
}
static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
+ return FIELD_EX32_IDREG(id, ID_MMFR4, AC2) != 0;
}
static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
+ return FIELD_EX32_IDREG(id, ID_MMFR4, CCIDX) != 0;
}
static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
+ return FIELD_EX32_IDREG(id, ID_MMFR4, XNX) != 0;
}
static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1;
+ return FIELD_EX32_IDREG(id, ID_MMFR4, EVT) >= 1;
}
static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2;
+ return FIELD_EX32_IDREG(id, ID_MMFR4, EVT) >= 2;
}
static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 496c7f9a3ce7..d27134f4a025 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1073,12 +1073,6 @@ struct ArchCPU {
* field by reading the value from the KVM vCPU.
*/
struct ARMISARegisters {
- uint32_t id_mmfr0;
- uint32_t id_mmfr1;
- uint32_t id_mmfr2;
- uint32_t id_mmfr3;
- uint32_t id_mmfr4;
- uint32_t id_mmfr5;
uint32_t mvfr0;
uint32_t mvfr1;
uint32_t mvfr2;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 292d09fb8e9b..9769401a8585 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -656,10 +656,10 @@ static void aarch64_a57_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x00011011);
SET_IDREG(isar, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x10101105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
+ SET_IDREG(isar, ID_MMFR0, 0x10101105);
+ SET_IDREG(isar, ID_MMFR1, 0x40000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01260000);
+ SET_IDREG(isar, ID_MMFR3, 0x02102211);
SET_IDREG(isar, ID_ISAR0, 0x02101110);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232042);
@@ -718,10 +718,10 @@ static void aarch64_a53_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x00011011);
SET_IDREG(isar, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x10101105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
+ SET_IDREG(isar, ID_MMFR0, 0x10101105);
+ SET_IDREG(isar, ID_MMFR1, 0x40000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01260000);
+ SET_IDREG(isar, ID_MMFR3, 0x02102211);
SET_IDREG(isar, ID_ISAR0, 0x02101110);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232042);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 69e9e681d21d..48b8dd541f3a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7808,22 +7808,22 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_mmfr0 },
+ .resetvalue = GET_IDREG(isar, ID_MMFR0)},
{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_mmfr1 },
+ .resetvalue = GET_IDREG(isar, ID_MMFR1)},
{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_mmfr2 },
+ .resetvalue = GET_IDREG(isar, ID_MMFR2)},
{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_mmfr3 },
+ .resetvalue = GET_IDREG(isar, ID_MMFR3)},
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
@@ -7858,7 +7858,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_mmfr4 },
+ .resetvalue = GET_IDREG(isar, ID_MMFR4)},
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
@@ -8138,7 +8138,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_mmfr5 },
+ .resetvalue = GET_IDREG(isar, ID_MMFR5)},
{ .name = "RES_0_C0_C3_7", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 1f7b8d40f002..8491f42a18d2 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -374,14 +374,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR0_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_DFR0_EL1_IDX);
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
- ARM64_SYS_REG(3, 0, 0, 1, 4));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
- ARM64_SYS_REG(3, 0, 0, 1, 5));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
- ARM64_SYS_REG(3, 0, 0, 1, 6));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
- ARM64_SYS_REG(3, 0, 0, 1, 7));
+ err |= get_host_cpu_reg(fd, ahcf, ID_MMFR0_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_MMFR1_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_MMFR2_EL1_IDX);
+ err |= get_host_cpu_reg(fd, ahcf, ID_MMFR3_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_ISAR0_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_ISAR1_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_ISAR2_EL1_IDX);
@@ -389,8 +385,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err |= get_host_cpu_reg(fd, ahcf, ID_ISAR4_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_ISAR5_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_ISAR6_EL1_IDX);
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
- ARM64_SYS_REG(3, 0, 0, 2, 6));
+ err |= get_host_cpu_reg(fd, ahcf, ID_MMFR4_EL1_IDX);
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
ARM64_SYS_REG(3, 0, 0, 3, 0));
@@ -400,8 +395,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ARM64_SYS_REG(3, 0, 0, 3, 2));
err |= get_host_cpu_reg(fd, ahcf, ID_PFR2_EL1_IDX);
err |= get_host_cpu_reg(fd, ahcf, ID_DFR1_EL1_IDX);
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5,
- ARM64_SYS_REG(3, 0, 0, 3, 6));
+ err |= get_host_cpu_reg(fd, ahcf, ID_MMFR5_EL1_IDX);
/*
* DBGDIDR is a bit complicated because the kernel doesn't
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index eb4e9653bfb6..0cb8dbcbbe8d 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -63,10 +63,10 @@ static void cortex_m0_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x00000200);
SET_IDREG(isar, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00000030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x00000000;
- cpu->isar.id_mmfr3 = 0x00000000;
+ SET_IDREG(isar, ID_MMFR0, 0x00000030);
+ SET_IDREG(isar, ID_MMFR1, 0x00000000);
+ SET_IDREG(isar, ID_MMFR2, 0x00000000);
+ SET_IDREG(isar, ID_MMFR3, 0x00000000);
SET_IDREG(isar, ID_ISAR0, 0x01141110);
SET_IDREG(isar, ID_ISAR1, 0x02111000);
SET_IDREG(isar, ID_ISAR2, 0x21112231);
@@ -89,10 +89,10 @@ static void cortex_m3_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x00000200);
SET_IDREG(isar, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00000030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x00000000;
- cpu->isar.id_mmfr3 = 0x00000000;
+ SET_IDREG(isar, ID_MMFR0, 0x00000030);
+ SET_IDREG(isar, ID_MMFR1, 0x00000000);
+ SET_IDREG(isar, ID_MMFR2, 0x00000000);
+ SET_IDREG(isar, ID_MMFR3, 0x00000000);
SET_IDREG(isar, ID_ISAR0, 0x01141110);
SET_IDREG(isar, ID_ISAR1, 0x02111000);
SET_IDREG(isar, ID_ISAR2, 0x21112231);
@@ -120,10 +120,10 @@ static void cortex_m4_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x00000200);
SET_IDREG(isar, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00000030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x00000000;
- cpu->isar.id_mmfr3 = 0x00000000;
+ SET_IDREG(isar, ID_MMFR0, 0x00000030);
+ SET_IDREG(isar, ID_MMFR1, 0x00000000);
+ SET_IDREG(isar, ID_MMFR2, 0x00000000);
+ SET_IDREG(isar, ID_MMFR3, 0x00000000);
SET_IDREG(isar, ID_ISAR0, 0x01141110);
SET_IDREG(isar, ID_ISAR1, 0x02111000);
SET_IDREG(isar, ID_ISAR2, 0x21112231);
@@ -151,10 +151,10 @@ static void cortex_m7_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x00000200);
SET_IDREG(isar, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00100030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01000000;
- cpu->isar.id_mmfr3 = 0x00000000;
+ SET_IDREG(isar, ID_MMFR0, 0x00100030);
+ SET_IDREG(isar, ID_MMFR1, 0x00000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01000000);
+ SET_IDREG(isar, ID_MMFR3, 0x00000000);
SET_IDREG(isar, ID_ISAR0, 0x01101110);
SET_IDREG(isar, ID_ISAR1, 0x02112000);
SET_IDREG(isar, ID_ISAR2, 0x20232231);
@@ -184,10 +184,10 @@ static void cortex_m33_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x00000210);
SET_IDREG(isar, ID_DFR0, 0x00200000);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00101F40;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01000000;
- cpu->isar.id_mmfr3 = 0x00000000;
+ SET_IDREG(isar, ID_MMFR0, 0x00101F40);
+ SET_IDREG(isar, ID_MMFR1, 0x00000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01000000);
+ SET_IDREG(isar, ID_MMFR3, 0x00000000);
SET_IDREG(isar, ID_ISAR0, 0x01101110);
SET_IDREG(isar, ID_ISAR1, 0x02212000);
SET_IDREG(isar, ID_ISAR2, 0x20232232);
@@ -222,10 +222,10 @@ static void cortex_m55_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x00000230);
SET_IDREG(isar, ID_DFR0, 0x10200000);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00111040;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01000000;
- cpu->isar.id_mmfr3 = 0x00000011;
+ SET_IDREG(isar, ID_MMFR0, 0x00111040);
+ SET_IDREG(isar, ID_MMFR1, 0x00000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01000000);
+ SET_IDREG(isar, ID_MMFR3, 0x00000011);
SET_IDREG(isar, ID_ISAR0, 0x01103110);
SET_IDREG(isar, ID_ISAR1, 0x02212000);
SET_IDREG(isar, ID_ISAR2, 0x20232232);
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 191b602c8c65..1558425594ee 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -55,21 +55,17 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
cpu->isar.mvfr2 = t;
- t = cpu->isar.id_mmfr3;
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
- cpu->isar.id_mmfr3 = t;
+ FIELD_DP32_IDREG(isar, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
- t = cpu->isar.id_mmfr4;
+ t = GET_IDREG(isar, ID_MMFR4);
t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */
t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
- cpu->isar.id_mmfr4 = t;
+ SET_IDREG(isar, ID_MMFR4, t);
- t = cpu->isar.id_mmfr5;
- t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
- cpu->isar.id_mmfr5 = t;
+ FIELD_DP32_IDREG(isar, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
t = GET_IDREG(isar, ID_PFR0);
t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
@@ -230,9 +226,9 @@ static void arm1136_r2_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x1);
SET_IDREG(isar, ID_DFR0, 0x2);
cpu->id_afr0 = 0x3;
- cpu->isar.id_mmfr0 = 0x01130003;
- cpu->isar.id_mmfr1 = 0x10030302;
- cpu->isar.id_mmfr2 = 0x01222110;
+ SET_IDREG(isar, ID_MMFR0, 0x01130003);
+ SET_IDREG(isar, ID_MMFR1, 0x10030302);
+ SET_IDREG(isar, ID_MMFR2, 0x01222110);
SET_IDREG(isar, ID_ISAR0, 0x00140011);
SET_IDREG(isar, ID_ISAR1, 0x12002111);
SET_IDREG(isar, ID_ISAR2, 0x11231111);
@@ -262,9 +258,9 @@ static void arm1136_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x1);
SET_IDREG(isar, ID_DFR0, 0x2);
cpu->id_afr0 = 0x3;
- cpu->isar.id_mmfr0 = 0x01130003;
- cpu->isar.id_mmfr1 = 0x10030302;
- cpu->isar.id_mmfr2 = 0x01222110;
+ SET_IDREG(isar, ID_MMFR0, 0x01130003);
+ SET_IDREG(isar, ID_MMFR1, 0x10030302);
+ SET_IDREG(isar, ID_MMFR2, 0x01222110);
SET_IDREG(isar, ID_ISAR0, 0x00140011);
SET_IDREG(isar, ID_ISAR1, 0x12002111);
SET_IDREG(isar, ID_ISAR2, 0x11231111);
@@ -295,9 +291,9 @@ static void arm1176_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x11);
SET_IDREG(isar, ID_DFR0, 0x33);
cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x01130003;
- cpu->isar.id_mmfr1 = 0x10030302;
- cpu->isar.id_mmfr2 = 0x01222100;
+ SET_IDREG(isar, ID_MMFR0, 0x01130003);
+ SET_IDREG(isar, ID_MMFR1, 0x10030302);
+ SET_IDREG(isar, ID_MMFR2, 0x01222100);
SET_IDREG(isar, ID_ISAR0, 0x0140011);
SET_IDREG(isar, ID_ISAR1, 0x12002111);
SET_IDREG(isar, ID_ISAR2, 0x11231121);
@@ -325,9 +321,9 @@ static void arm11mpcore_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x1);
SET_IDREG(isar, ID_DFR0, 0);
cpu->id_afr0 = 0x2;
- cpu->isar.id_mmfr0 = 0x01100103;
- cpu->isar.id_mmfr1 = 0x10020302;
- cpu->isar.id_mmfr2 = 0x01222000;
+ SET_IDREG(isar, ID_MMFR0, 0x01100103);
+ SET_IDREG(isar, ID_MMFR1, 0x10020302);
+ SET_IDREG(isar, ID_MMFR2, 0x01222000);
SET_IDREG(isar, ID_ISAR0, 0x00100011);
SET_IDREG(isar, ID_ISAR1, 0x12002111);
SET_IDREG(isar, ID_ISAR2, 0x11221011);
@@ -365,10 +361,10 @@ static void cortex_a8_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x11);
SET_IDREG(isar, ID_DFR0, 0x400);
cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x31100003;
- cpu->isar.id_mmfr1 = 0x20000000;
- cpu->isar.id_mmfr2 = 0x01202000;
- cpu->isar.id_mmfr3 = 0x11;
+ SET_IDREG(isar, ID_MMFR0, 0x31100003);
+ SET_IDREG(isar, ID_MMFR1, 0x20000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01202000);
+ SET_IDREG(isar, ID_MMFR3, 0x11);
SET_IDREG(isar, ID_ISAR0, 0x00101111);
SET_IDREG(isar, ID_ISAR1, 0x12112111);
SET_IDREG(isar, ID_ISAR2, 0x21232031);
@@ -441,10 +437,10 @@ static void cortex_a9_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x11);
SET_IDREG(isar, ID_DFR0, 0x000);
cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x00100103;
- cpu->isar.id_mmfr1 = 0x20000000;
- cpu->isar.id_mmfr2 = 0x01230000;
- cpu->isar.id_mmfr3 = 0x00002111;
+ SET_IDREG(isar, ID_MMFR0, 0x00100103);
+ SET_IDREG(isar, ID_MMFR1, 0x20000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01230000);
+ SET_IDREG(isar, ID_MMFR3, 0x00002111);
SET_IDREG(isar, ID_ISAR0, 0x00101111);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232041);
@@ -507,10 +503,10 @@ static void cortex_a7_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x00011011);
SET_IDREG(isar, ID_DFR0, 0x02010555);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x10101105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01240000;
- cpu->isar.id_mmfr3 = 0x02102211;
+ SET_IDREG(isar, ID_MMFR0, 0x10101105);
+ SET_IDREG(isar, ID_MMFR1, 0x40000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01240000);
+ SET_IDREG(isar, ID_MMFR3, 0x02102211);
/*
* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
* table 4-41 gives 0x02101110, which includes the arm div insns.
@@ -559,10 +555,10 @@ static void cortex_a15_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x00011011);
SET_IDREG(isar, ID_DFR0, 0x02010555);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x20000000;
- cpu->isar.id_mmfr2 = 0x01240000;
- cpu->isar.id_mmfr3 = 0x02102211;
+ SET_IDREG(isar, ID_MMFR0, 0x10201105);
+ SET_IDREG(isar, ID_MMFR1, 0x20000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01240000);
+ SET_IDREG(isar, ID_MMFR3, 0x02102211);
SET_IDREG(isar, ID_ISAR0, 0x02101110);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232041);
@@ -603,10 +599,10 @@ static void cortex_r5_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x001);
SET_IDREG(isar, ID_DFR0, 0x010400);
cpu->id_afr0 = 0x0;
- cpu->isar.id_mmfr0 = 0x0210030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01200000;
- cpu->isar.id_mmfr3 = 0x0211;
+ SET_IDREG(isar, ID_MMFR0, 0x0210030);
+ SET_IDREG(isar, ID_MMFR1, 0x00000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01200000);
+ SET_IDREG(isar, ID_MMFR3, 0x0211);
SET_IDREG(isar, ID_ISAR0, 0x02101111);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232141);
@@ -750,11 +746,11 @@ static void cortex_r52_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x10111001);
SET_IDREG(isar, ID_DFR0, 0x03010006);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00211040;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01200000;
- cpu->isar.id_mmfr3 = 0xf0102211;
- cpu->isar.id_mmfr4 = 0x00000010;
+ SET_IDREG(isar, ID_MMFR0, 0x00211040);
+ SET_IDREG(isar, ID_MMFR1, 0x40000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01200000);
+ SET_IDREG(isar, ID_MMFR3, 0xf0102211);
+ SET_IDREG(isar, ID_MMFR4, 0x00000010);
SET_IDREG(isar, ID_ISAR0, 0x02101110);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232142);
@@ -982,10 +978,10 @@ static void arm_max_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x00011011);
SET_IDREG(isar, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x10101105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
+ SET_IDREG(isar, ID_MMFR0, 0x10101105);
+ SET_IDREG(isar, ID_MMFR1, 0x40000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01260000);
+ SET_IDREG(isar, ID_MMFR3, 0x02102211);
SET_IDREG(isar, ID_ISAR0, 0x02101110);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232042);
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 738826a7bf97..22297cebab77 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -53,10 +53,10 @@ static void aarch64_a35_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x00011011);
SET_IDREG(isar, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
+ SET_IDREG(isar, ID_MMFR0, 0x10201105);
+ SET_IDREG(isar, ID_MMFR1, 0x40000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01260000);
+ SET_IDREG(isar, ID_MMFR3, 0x02102211);
SET_IDREG(isar, ID_ISAR0, 0x02101110);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232042);
@@ -236,11 +236,11 @@ static void aarch64_a55_initfn(Object *obj)
SET_IDREG(isar, ID_ISAR4, 0x00011142);
SET_IDREG(isar, ID_ISAR5, 0x01011121);
SET_IDREG(isar, ID_ISAR6, 0x00000010);
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x00021110;
+ SET_IDREG(isar, ID_MMFR0, 0x10201105);
+ SET_IDREG(isar, ID_MMFR1, 0x40000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01260000);
+ SET_IDREG(isar, ID_MMFR3, 0x02122211);
+ SET_IDREG(isar, ID_MMFR4, 0x00021110);
SET_IDREG(isar, ID_PFR0, 0x10010131);
SET_IDREG(isar, ID_PFR1, 0x00011011);
SET_IDREG(isar, ID_PFR2, 0x00000011);
@@ -299,10 +299,10 @@ static void aarch64_a72_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x00011011);
SET_IDREG(isar, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
+ SET_IDREG(isar, ID_MMFR0, 0x10201105);
+ SET_IDREG(isar, ID_MMFR1, 0x40000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01260000);
+ SET_IDREG(isar, ID_MMFR3, 0x02102211);
SET_IDREG(isar, ID_ISAR0, 0x02101110);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232042);
@@ -369,11 +369,11 @@ static void aarch64_a76_initfn(Object *obj)
SET_IDREG(isar, ID_ISAR4, 0x00010142);
SET_IDREG(isar, ID_ISAR5, 0x01011121);
SET_IDREG(isar, ID_ISAR6, 0x00000010);
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x00021110;
+ SET_IDREG(isar, ID_MMFR0, 0x10201105);
+ SET_IDREG(isar, ID_MMFR1, 0x40000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01260000);
+ SET_IDREG(isar, ID_MMFR3, 0x02122211);
+ SET_IDREG(isar, ID_MMFR4, 0x00021110);
SET_IDREG(isar, ID_PFR0, 0x10010131);
SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
SET_IDREG(isar, ID_PFR2, 0x00000011);
@@ -617,11 +617,11 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
SET_IDREG(isar, ID_ISAR4, 0x00010142);
SET_IDREG(isar, ID_ISAR5, 0x01011121);
SET_IDREG(isar, ID_ISAR6, 0x00000010);
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x00021110;
+ SET_IDREG(isar, ID_MMFR0, 0x10201105);
+ SET_IDREG(isar, ID_MMFR1, 0x40000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01260000);
+ SET_IDREG(isar, ID_MMFR3, 0x02122211);
+ SET_IDREG(isar, ID_MMFR4, 0x00021110);
SET_IDREG(isar, ID_PFR0, 0x10010131);
SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
SET_IDREG(isar, ID_PFR2, 0x00000011);
@@ -696,11 +696,11 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
SET_IDREG(isar, ID_ISAR4, 0x00010142);
SET_IDREG(isar, ID_ISAR5, 0x11011121);
SET_IDREG(isar, ID_ISAR6, 0x01100111);
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x01021110;
+ SET_IDREG(isar, ID_MMFR0, 0x10201105);
+ SET_IDREG(isar, ID_MMFR1, 0x40000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01260000);
+ SET_IDREG(isar, ID_MMFR3, 0x02122211);
+ SET_IDREG(isar, ID_MMFR4, 0x01021110);
SET_IDREG(isar, ID_PFR0, 0x21110131);
SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
SET_IDREG(isar, ID_PFR2, 0x00000011);
@@ -906,17 +906,17 @@ static void aarch64_a710_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
SET_IDREG(isar, ID_DFR0, 0x16011099);
cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
+ SET_IDREG(isar, ID_MMFR0, 0x10201105);
+ SET_IDREG(isar, ID_MMFR1, 0x40000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01260000);
+ SET_IDREG(isar, ID_MMFR3, 0x02122211);
SET_IDREG(isar, ID_ISAR0, 0x02101110);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232042);
SET_IDREG(isar, ID_ISAR3, 0x01112131);
SET_IDREG(isar, ID_ISAR4, 0x00010142);
SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */
- cpu->isar.id_mmfr4 = 0x21021110;
+ SET_IDREG(isar, ID_MMFR4, 0x21021110);
SET_IDREG(isar, ID_ISAR6, 0x01111111);
cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111;
@@ -1009,17 +1009,17 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */
SET_IDREG(isar, ID_DFR0, 0x16011099);
cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
+ SET_IDREG(isar, ID_MMFR0, 0x10201105);
+ SET_IDREG(isar, ID_MMFR1, 0x40000000);
+ SET_IDREG(isar, ID_MMFR2, 0x01260000);
+ SET_IDREG(isar, ID_MMFR3, 0x02122211);
SET_IDREG(isar, ID_ISAR0, 0x02101110);
SET_IDREG(isar, ID_ISAR1, 0x13112111);
SET_IDREG(isar, ID_ISAR2, 0x21232042);
SET_IDREG(isar, ID_ISAR3, 0x01112131);
SET_IDREG(isar, ID_ISAR4, 0x00010142);
SET_IDREG(isar, ID_ISAR5, 0x11011121); /* with Crypto */
- cpu->isar.id_mmfr4 = 0x01021110;
+ SET_IDREG(isar, ID_MMFR4, 0x01021110);
SET_IDREG(isar, ID_ISAR6, 0x01111111);
cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111;
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH for-10.1 v5 12/13] arm/cpu: Add sysreg generation scripts
2025-04-09 14:42 [PATCH for-10.1 v5 00/13] arm: rework id register storage Cornelia Huck
` (10 preceding siblings ...)
2025-04-09 14:43 ` [PATCH for-10.1 v5 11/13] arm/cpu: Store id_mmfr0-5 " Cornelia Huck
@ 2025-04-09 14:43 ` Cornelia Huck
2025-04-09 14:43 ` [PATCH for-10.1 v5 13/13] arm/cpu: switch to a generated cpu-sysregs.h.inc Cornelia Huck
2025-04-28 16:43 ` [PATCH for-10.1 v5 00/13] arm: rework id register storage Eric Auger
13 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-04-09 14:43 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Introduce scripts that automate the generation of system register
definitions from a given linux source tree arch/arm64/tools/sysreg.
Invocation of
./update-aarch64-sysreg-code.sh $PATH_TO_LINUX_SOURCE_TREE
in scripts directory generates target/arm/cpu-sysregs.h.inc
containing defines for all system registers.
[CH: update to handle current kernel sysregs structure, and to emit
the re-worked register structures; cpu properties will be added
later]
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
| 35 +++++++++++++++++++++++++++
scripts/update-aarch64-sysreg-code.sh | 25 +++++++++++++++++++
2 files changed, 60 insertions(+)
create mode 100755 scripts/gen-cpu-sysregs-header.awk
create mode 100755 scripts/update-aarch64-sysreg-code.sh
--git a/scripts/gen-cpu-sysregs-header.awk b/scripts/gen-cpu-sysregs-header.awk
new file mode 100755
index 000000000000..b6b207e3c0fd
--- /dev/null
+++ b/scripts/gen-cpu-sysregs-header.awk
@@ -0,0 +1,35 @@
+#!/bin/awk -f
+# SPDX-License-Identifier: GPL-2.0
+# gen-cpu-sysregs-header.awk: arm64 sysreg header include generator
+#
+# Usage: awk -f gen-cpu-sysregs-header.awk $LINUX_PATH/arch/arm64/tools/sysreg
+
+BEGIN {
+ print ""
+} END {
+ print ""
+}
+
+# skip blank lines and comment lines
+/^$/ { next }
+/^[\t ]*#/ { next }
+
+/^Sysreg\t/ || /^Sysreg /{
+
+ reg = $2
+ op0 = $3
+ op1 = $4
+ crn = $5
+ crm = $6
+ op2 = $7
+
+ if (op0 == 3 && (op1>=0 && op1<=3) && crn==0 && (crm>=0 && crm<=7) && (op2>=0 && op2<=7)) {
+ print "DEF("reg", "op0", "op1", "crn", "crm", "op2")"
+ }
+ next
+}
+
+{
+ /* skip all other lines */
+ next
+}
diff --git a/scripts/update-aarch64-sysreg-code.sh b/scripts/update-aarch64-sysreg-code.sh
new file mode 100755
index 000000000000..721f41a9a516
--- /dev/null
+++ b/scripts/update-aarch64-sysreg-code.sh
@@ -0,0 +1,25 @@
+#!/bin/sh -e
+#
+# Update target/arm/cpu-sysregs.h
+# from a linux source tree (arch/arm64/tools/sysreg)
+#
+# Copyright Red Hat, Inc. 2024
+#
+# Authors:
+# Eric Auger <eric.auger@redhat.com>
+#
+
+linux="$1"
+output="$PWD"
+
+if [ -z "$linux" ] || ! [ -d "$linux" ]; then
+ cat << EOF
+usage: update-aarch64-sysreg-code.sh LINUX_PATH
+
+LINUX_PATH Linux kernel directory to obtain the headers from
+EOF
+ exit 1
+fi
+
+awk -f gen-cpu-sysregs-header.awk \
+ $linux/arch/arm64/tools/sysreg > ../target/arm/cpu-sysregs.h.inc
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH for-10.1 v5 13/13] arm/cpu: switch to a generated cpu-sysregs.h.inc
2025-04-09 14:42 [PATCH for-10.1 v5 00/13] arm: rework id register storage Cornelia Huck
` (11 preceding siblings ...)
2025-04-09 14:43 ` [PATCH for-10.1 v5 12/13] arm/cpu: Add sysreg generation scripts Cornelia Huck
@ 2025-04-09 14:43 ` Cornelia Huck
2025-04-28 16:38 ` Eric Auger
2025-04-28 16:43 ` [PATCH for-10.1 v5 00/13] arm: rework id register storage Eric Auger
13 siblings, 1 reply; 29+ messages in thread
From: Cornelia Huck @ 2025-04-09 14:43 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
Generated against Linux 6.14-rc1.
Reviewed-by: Sebastian Ott <sebott@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-sysregs.h.inc | 43 +++++++++++++++++++++++++-----------
1 file changed, 30 insertions(+), 13 deletions(-)
diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
index 6c9f9981cc5d..02aae133eb67 100644
--- a/target/arm/cpu-sysregs.h.inc
+++ b/target/arm/cpu-sysregs.h.inc
@@ -1,18 +1,8 @@
-DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
-DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
-DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)
-DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
-DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
-DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
-DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)
-DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2)
-DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0)
-DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)
-DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)
-DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3)
+
DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0)
DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1)
DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2)
+DEF(ID_AFR0_EL1, 3, 0, 0, 1, 3)
DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4)
DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5)
DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6)
@@ -23,13 +13,40 @@ DEF(ID_ISAR2_EL1, 3, 0, 0, 2, 2)
DEF(ID_ISAR3_EL1, 3, 0, 0, 2, 3)
DEF(ID_ISAR4_EL1, 3, 0, 0, 2, 4)
DEF(ID_ISAR5_EL1, 3, 0, 0, 2, 5)
-DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6)
DEF(ID_ISAR6_EL1, 3, 0, 0, 2, 7)
+DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6)
DEF(MVFR0_EL1, 3, 0, 0, 3, 0)
DEF(MVFR1_EL1, 3, 0, 0, 3, 1)
DEF(MVFR2_EL1, 3, 0, 0, 3, 2)
DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4)
DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5)
DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6)
+DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
+DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
+DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2)
DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4)
+DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)
+DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7)
+DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
+DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
+DEF(ID_AA64DFR2_EL1, 3, 0, 0, 5, 2)
+DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4)
+DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5)
+DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
+DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)
+DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2)
+DEF(ID_AA64ISAR3_EL1, 3, 0, 0, 6, 3)
+DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0)
+DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)
+DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)
+DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3)
+DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4)
+DEF(CCSIDR_EL1, 3, 1, 0, 0, 0)
+DEF(CLIDR_EL1, 3, 1, 0, 0, 1)
+DEF(CCSIDR2_EL1, 3, 1, 0, 0, 2)
+DEF(GMID_EL1, 3, 1, 0, 0, 4)
+DEF(SMIDR_EL1, 3, 1, 0, 0, 6)
+DEF(CSSELR_EL1, 3, 2, 0, 0, 0)
DEF(CTR_EL0, 3, 3, 0, 0, 1)
+DEF(DCZID_EL0, 3, 3, 0, 0, 7)
+
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH for-10.1 v5 13/13] arm/cpu: switch to a generated cpu-sysregs.h.inc
2025-04-09 14:43 ` [PATCH for-10.1 v5 13/13] arm/cpu: switch to a generated cpu-sysregs.h.inc Cornelia Huck
@ 2025-04-28 16:38 ` Eric Auger
0 siblings, 0 replies; 29+ messages in thread
From: Eric Auger @ 2025-04-28 16:38 UTC (permalink / raw)
To: Cornelia Huck, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini
On 4/9/25 4:43 PM, Cornelia Huck wrote:
> Generated against Linux 6.14-rc1.
>
> Reviewed-by: Sebastian Ott <sebott@redhat.com>
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Eric
> ---
> target/arm/cpu-sysregs.h.inc | 43 +++++++++++++++++++++++++-----------
> 1 file changed, 30 insertions(+), 13 deletions(-)
>
> diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
> index 6c9f9981cc5d..02aae133eb67 100644
> --- a/target/arm/cpu-sysregs.h.inc
> +++ b/target/arm/cpu-sysregs.h.inc
> @@ -1,18 +1,8 @@
> -DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
> -DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
> -DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)
> -DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
> -DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
> -DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
> -DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)
> -DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2)
> -DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0)
> -DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)
> -DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)
> -DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3)
> +
> DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0)
> DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1)
> DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2)
> +DEF(ID_AFR0_EL1, 3, 0, 0, 1, 3)
> DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4)
> DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5)
> DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6)
> @@ -23,13 +13,40 @@ DEF(ID_ISAR2_EL1, 3, 0, 0, 2, 2)
> DEF(ID_ISAR3_EL1, 3, 0, 0, 2, 3)
> DEF(ID_ISAR4_EL1, 3, 0, 0, 2, 4)
> DEF(ID_ISAR5_EL1, 3, 0, 0, 2, 5)
> -DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6)
> DEF(ID_ISAR6_EL1, 3, 0, 0, 2, 7)
> +DEF(ID_MMFR4_EL1, 3, 0, 0, 2, 6)
> DEF(MVFR0_EL1, 3, 0, 0, 3, 0)
> DEF(MVFR1_EL1, 3, 0, 0, 3, 1)
> DEF(MVFR2_EL1, 3, 0, 0, 3, 2)
> DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4)
> DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5)
> DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6)
> +DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
> +DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
> +DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2)
> DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4)
> +DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)
> +DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7)
> +DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
> +DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
> +DEF(ID_AA64DFR2_EL1, 3, 0, 0, 5, 2)
> +DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4)
> +DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5)
> +DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
> +DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)
> +DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2)
> +DEF(ID_AA64ISAR3_EL1, 3, 0, 0, 6, 3)
> +DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0)
> +DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1)
> +DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2)
> +DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3)
> +DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4)
> +DEF(CCSIDR_EL1, 3, 1, 0, 0, 0)
> +DEF(CLIDR_EL1, 3, 1, 0, 0, 1)
> +DEF(CCSIDR2_EL1, 3, 1, 0, 0, 2)
> +DEF(GMID_EL1, 3, 1, 0, 0, 4)
> +DEF(SMIDR_EL1, 3, 1, 0, 0, 6)
> +DEF(CSSELR_EL1, 3, 2, 0, 0, 0)
> DEF(CTR_EL0, 3, 3, 0, 0, 1)
> +DEF(DCZID_EL0, 3, 3, 0, 0, 7)
> +
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH for-10.1 v5 00/13] arm: rework id register storage
2025-04-09 14:42 [PATCH for-10.1 v5 00/13] arm: rework id register storage Cornelia Huck
` (12 preceding siblings ...)
2025-04-09 14:43 ` [PATCH for-10.1 v5 13/13] arm/cpu: switch to a generated cpu-sysregs.h.inc Cornelia Huck
@ 2025-04-28 16:43 ` Eric Auger
2025-04-29 10:05 ` Cornelia Huck
13 siblings, 1 reply; 29+ messages in thread
From: Eric Auger @ 2025-04-28 16:43 UTC (permalink / raw)
To: Cornelia Huck, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini
Hi Connie,
On 4/9/25 4:42 PM, Cornelia Huck wrote:
> Just a quick respin to fix a missed conversion in hvf.c.
>
> Also available at
> https://gitlab.com/cohuck/qemu/-/commits/arm-rework-idreg-storage-v5
I reviewed it again - I can't send any R-b through since I am co-author
;-) - and I spotted few conversion mistakes (I am most probably the one
to blame here sorry)
Once those fixed, I think we should be good.
Eric
>
> <v4 cover letter>
> Next iteration of the id register patches; only small changes.
>
> Changed from v3:
> - added R-bs (thanks!)
> - added missing SPDX header
> - merged patch introducing accessors for kvm to the first user
> - skip over sysregs outside of the id register range when generating
> register definitions again
>
> Also available at
> https://gitlab.com/cohuck/qemu/-/commits/arm-rework-idreg-storage-v4
>
> <v3 cover letter>
> Yet another update of the id register series, less changes this time
> around.
>
> Changed from v2:
> - changed generation of the various register defines via the "DEF"
> magic suggested by Richard
> - some kvm-only code moved to kvm.c; some code potentially useful to
> non-kvm code stayed out of there (the cpu model code will make use
> of it, and that one should be extendable outside of kvm -- a
> revised version of those patches is still in the works, but I'll be
> off for a few days and rather wanted to get this one out first)
>
> Also available at
> https://gitlab.com/cohuck/qemu/-/commits/arm-rework-idreg-storage-v3
>
> <v2 cover letter>
>
> Changed from v1:
> - Noticed that we missed the hvf code. Converted, compiled, but not tested
> as I'm lacking an environment for testing.
> - Hopefully incorporated most of the suggested changes -- if I missed
> something, it was unintentional unless mentioned below.
> - fixed repeated inclusion of definitions
> - hopefully made macros more robust
> - removed distinction between reading 32/64 values, which was mostly
> adding churn for little value
> - postponed generating property definitions to the cpu model patches,
> where they are actually used
> - juggled hunks and moved them to the right patches
> - fixed some typos
> - rebased to a more recent code base
>
> NOT changed from v1:
> - definitions are still generated from the Linux sysregs file
> - I still think updating the generated files on demand (so that we can
> double check the result) is the right thing to do
> - I'm open to changing the source of the definitions from the sysregs
> file to the JSON definitions published by Arm; however, I first wanted
> to get the code using it right -- we can switch out the code generating
> the file to use a different source easily later on, and I'd also like
> to steal parts of the script from Linux once integrated (which I think
> hasn't happened yet?)
>
> <v1 cover letter>
>
> [Note: I've kept the cc list from the last round of cpu model patches;
> so if you're confused as to why you're cc:ed here, take it as a
> heads-up that a new cpu model series will come along soon]
>
> This patch series contains patches extracted from the larger cpu model
> series (RFC v2 last posted at
> https://lore.kernel.org/qemu-devel/20241206112213.88394-1-cohuck@redhat.com/)
> and aims at providing a base upon which we can continue with building
> support for cpu models, but which is hopefully already an improvement
> on its own.
>
> Main changes from the patches in that series include:
> - post-pone the changes to handle KVM writable ID registers for cpu models
> (I have a series including that on top of this one)
> - change how we store the list of ID registers, and access them
> basically, use an enum for indexing, and an enum doing encodings in a
> pattern similar to cpregs
> - move some hunks to different patches
> - update the scripts to generate the register descriptions, and run
> them against a recent Linux sysregs file
>
> What I've kept:
> - generating the register descriptions from the Linux sysregs file
> I think that file is still our best bet to generate the descriptions
> easily, and updating the definitions is a manual step that can be checked
> for unintended changes
> - most of the hard work that Eric had been doing; all new bugs in there
> are my own :)
>
> </v1 cover letter>
> </v2 cover letter>
> </v3 cover letter>
> </v4 cover letter>
>
> Cornelia Huck (1):
> arm/cpu: switch to a generated cpu-sysregs.h.inc
>
> Eric Auger (12):
> arm/cpu: Add sysreg definitions in cpu-sysregs.h
> arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays
> arm/cpu: Store aa64isar1/2 into the idregs array
> arm/cpu: Store aa64pfr0/1 into the idregs array
> arm/cpu: Store aa64mmfr0-3 into the idregs array
> arm/cpu: Store aa64dfr0/1 into the idregs array
> arm/cpu: Store aa64smfr0 into the idregs array
> arm/cpu: Store id_isar0-7 into the idregs array
> arm/cpu: Store id_pfr0/1/2 into the idregs array
> arm/cpu: Store id_dfr0/1 into the idregs array
> arm/cpu: Store id_mmfr0-5 into the idregs array
> arm/cpu: Add sysreg generation scripts
>
> hw/intc/armv7m_nvic.c | 27 +-
> scripts/gen-cpu-sysregs-header.awk | 35 ++
> scripts/update-aarch64-sysreg-code.sh | 25 ++
> target/arm/cpu-features.h | 317 +++++++++---------
> target/arm/cpu-sysregs.h | 46 +++
> target/arm/cpu-sysregs.h.inc | 52 +++
> target/arm/cpu.c | 111 +++----
> target/arm/cpu.h | 80 +++--
> target/arm/cpu64.c | 128 +++----
> target/arm/helper.c | 68 ++--
> target/arm/hvf/hvf.c | 39 ++-
> target/arm/internals.h | 6 +-
> target/arm/kvm.c | 129 ++++----
> target/arm/ptw.c | 6 +-
> target/arm/tcg/cpu-v7m.c | 174 +++++-----
> target/arm/tcg/cpu32.c | 320 +++++++++---------
> target/arm/tcg/cpu64.c | 460 +++++++++++++-------------
> 17 files changed, 1103 insertions(+), 920 deletions(-)
> create mode 100755 scripts/gen-cpu-sysregs-header.awk
> create mode 100755 scripts/update-aarch64-sysreg-code.sh
> create mode 100644 target/arm/cpu-sysregs.h
> create mode 100644 target/arm/cpu-sysregs.h.inc
>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH for-10.1 v5 00/13] arm: rework id register storage
2025-04-28 16:43 ` [PATCH for-10.1 v5 00/13] arm: rework id register storage Eric Auger
@ 2025-04-29 10:05 ` Cornelia Huck
0 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-04-29 10:05 UTC (permalink / raw)
To: eric.auger, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, agraf
Cc: shahuang, mark.rutland, philmd, pbonzini
On Mon, Apr 28 2025, Eric Auger <eric.auger@redhat.com> wrote:
> Hi Connie,
>
> On 4/9/25 4:42 PM, Cornelia Huck wrote:
>> Just a quick respin to fix a missed conversion in hvf.c.
>>
>> Also available at
>> https://gitlab.com/cohuck/qemu/-/commits/arm-rework-idreg-storage-v5
>
> I reviewed it again - I can't send any R-b through since I am co-author
> ;-) - and I spotted few conversion mistakes (I am most probably the one
> to blame here sorry)
Oh, I think I'm perfectly capable of messing up on my own :)
>
> Once those fixed, I think we should be good.
Thanks for the review, I fixed things up and did fdarray[2] -> fd for
the few cases remaining at the end. Will probably repost after some
testing.
^ permalink raw reply [flat|nested] 29+ messages in thread