[PATCH v2 00/10] target/microblaze: Always use TARGET_LONG_BITS == 32

[PATCH v2 00/10] target/microblaze: Always use TARGET_LONG_BITS == 32

[Richard Henderson]

v1: https://lore.kernel.org/qemu-devel/20250212220155.1147144-1-richard.henderson@linaro.org/

Use out-of-line helpers to implement extended address memory ops.
With this, we can reduce TARGET_LONG_BITS to the more natural 32
for this 32-bit cpu.

Changes for v2:
  - Handle alignment check inline, where we can pre-test MSR_EE
    and cfg->unaligned_exceptions.
  - Add both big and little-endian helpers, selected at translation.


r~


Richard Henderson (10):
  target/microblaze: Split out mb_unaligned_access_internal
  target/microblaze: Introduce helper_unaligned_access
  target/microblaze: Split out mb_transaction_failed_internal
  target/microblaze: Implement extended address load/store out of line
  target/microblaze: Use uint64_t for CPUMBState.ear
  target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea
  target/microblaze: Fix printf format in mmu_translate
  target/microblaze: Use TARGET_LONG_BITS == 32 for system mode
  target/microblaze: Drop DisasContext.r0
  target/microblaze: Simplify compute_ldst_addr_type{a,b}

 target/microblaze/cpu.h                  |   2 +-
 target/microblaze/helper.h               |  22 ++--
 target/microblaze/helper.c               |  71 ++++++++-----
 target/microblaze/mmu.c                  |   3 +-
 target/microblaze/op_helper.c            | 110 ++++++++++++++-----
 target/microblaze/translate.c            | 128 ++++++++++++-----------
 configs/targets/microblaze-softmmu.mak   |   4 +-
 configs/targets/microblazeel-softmmu.mak |   4 +-
 8 files changed, 214 insertions(+), 130 deletions(-)

-- 
2.43.0

[PATCH v2 01/10] target/microblaze: Split out mb_unaligned_access_internal

[Richard Henderson]

Use an explicit 64-bit type for the address to store in EAR.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/helper.c | 64 +++++++++++++++++++++-----------------
 1 file changed, 36 insertions(+), 28 deletions(-)

diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 9203192483..5fe81e4b16 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -27,6 +27,42 @@
 #include "qemu/host-utils.h"
 #include "exec/log.h"
 
+
+G_NORETURN
+static void mb_unaligned_access_internal(CPUState *cs, uint64_t addr,
+                                         uintptr_t retaddr)
+{
+    CPUMBState *env = cpu_env(cs);
+    uint32_t esr, iflags;
+
+    /* Recover the pc and iflags from the corresponding insn_start.  */
+    cpu_restore_state(cs, retaddr);
+    iflags = env->iflags;
+
+    qemu_log_mask(CPU_LOG_INT,
+                  "Unaligned access addr=0x%" PRIx64 " pc=%x iflags=%x\n",
+                  addr, env->pc, iflags);
+
+    esr = ESR_EC_UNALIGNED_DATA;
+    if (likely(iflags & ESR_ESS_FLAG)) {
+        esr |= iflags & ESR_ESS_MASK;
+    } else {
+        qemu_log_mask(LOG_UNIMP, "Unaligned access without ESR_ESS_FLAG\n");
+    }
+
+    env->ear = addr;
+    env->esr = esr;
+    cs->exception_index = EXCP_HW_EXCP;
+    cpu_loop_exit(cs);
+}
+
+void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
+                                MMUAccessType access_type,
+                                int mmu_idx, uintptr_t retaddr)
+{
+    mb_unaligned_access_internal(cs, addr, retaddr);
+}
+
 #ifndef CONFIG_USER_ONLY
 static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu,
                                     MMUAccessType access_type)
@@ -269,31 +305,3 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 }
 
 #endif /* !CONFIG_USER_ONLY */
-
-void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
-                                MMUAccessType access_type,
-                                int mmu_idx, uintptr_t retaddr)
-{
-    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
-    uint32_t esr, iflags;
-
-    /* Recover the pc and iflags from the corresponding insn_start.  */
-    cpu_restore_state(cs, retaddr);
-    iflags = cpu->env.iflags;
-
-    qemu_log_mask(CPU_LOG_INT,
-                  "Unaligned access addr=" TARGET_FMT_lx " pc=%x iflags=%x\n",
-                  (target_ulong)addr, cpu->env.pc, iflags);
-
-    esr = ESR_EC_UNALIGNED_DATA;
-    if (likely(iflags & ESR_ESS_FLAG)) {
-        esr |= iflags & ESR_ESS_MASK;
-    } else {
-        qemu_log_mask(LOG_UNIMP, "Unaligned access without ESR_ESS_FLAG\n");
-    }
-
-    cpu->env.ear = addr;
-    cpu->env.esr = esr;
-    cs->exception_index = EXCP_HW_EXCP;
-    cpu_loop_exit(cs);
-}
-- 
2.43.0

Re: [PATCH v2 01/10] target/microblaze: Split out mb_unaligned_access_internal

[Edgar E. Iglesias]

On Sun, May 25, 2025 at 05:02:11PM +0100, Richard Henderson wrote:
> Use an explicit 64-bit type for the address to store in EAR.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>


> ---
>  target/microblaze/helper.c | 64 +++++++++++++++++++++-----------------
>  1 file changed, 36 insertions(+), 28 deletions(-)
> 
> diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
> index 9203192483..5fe81e4b16 100644
> --- a/target/microblaze/helper.c
> +++ b/target/microblaze/helper.c
> @@ -27,6 +27,42 @@
>  #include "qemu/host-utils.h"
>  #include "exec/log.h"
>  
> +
> +G_NORETURN
> +static void mb_unaligned_access_internal(CPUState *cs, uint64_t addr,
> +                                         uintptr_t retaddr)
> +{
> +    CPUMBState *env = cpu_env(cs);
> +    uint32_t esr, iflags;
> +
> +    /* Recover the pc and iflags from the corresponding insn_start.  */
> +    cpu_restore_state(cs, retaddr);
> +    iflags = env->iflags;
> +
> +    qemu_log_mask(CPU_LOG_INT,
> +                  "Unaligned access addr=0x%" PRIx64 " pc=%x iflags=%x\n",
> +                  addr, env->pc, iflags);
> +
> +    esr = ESR_EC_UNALIGNED_DATA;
> +    if (likely(iflags & ESR_ESS_FLAG)) {
> +        esr |= iflags & ESR_ESS_MASK;
> +    } else {
> +        qemu_log_mask(LOG_UNIMP, "Unaligned access without ESR_ESS_FLAG\n");
> +    }
> +
> +    env->ear = addr;
> +    env->esr = esr;
> +    cs->exception_index = EXCP_HW_EXCP;
> +    cpu_loop_exit(cs);
> +}
> +
> +void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> +                                MMUAccessType access_type,
> +                                int mmu_idx, uintptr_t retaddr)
> +{
> +    mb_unaligned_access_internal(cs, addr, retaddr);
> +}
> +
>  #ifndef CONFIG_USER_ONLY
>  static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu,
>                                      MMUAccessType access_type)
> @@ -269,31 +305,3 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
>  }
>  
>  #endif /* !CONFIG_USER_ONLY */
> -
> -void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> -                                MMUAccessType access_type,
> -                                int mmu_idx, uintptr_t retaddr)
> -{
> -    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> -    uint32_t esr, iflags;
> -
> -    /* Recover the pc and iflags from the corresponding insn_start.  */
> -    cpu_restore_state(cs, retaddr);
> -    iflags = cpu->env.iflags;
> -
> -    qemu_log_mask(CPU_LOG_INT,
> -                  "Unaligned access addr=" TARGET_FMT_lx " pc=%x iflags=%x\n",
> -                  (target_ulong)addr, cpu->env.pc, iflags);
> -
> -    esr = ESR_EC_UNALIGNED_DATA;
> -    if (likely(iflags & ESR_ESS_FLAG)) {
> -        esr |= iflags & ESR_ESS_MASK;
> -    } else {
> -        qemu_log_mask(LOG_UNIMP, "Unaligned access without ESR_ESS_FLAG\n");
> -    }
> -
> -    cpu->env.ear = addr;
> -    cpu->env.esr = esr;
> -    cs->exception_index = EXCP_HW_EXCP;
> -    cpu_loop_exit(cs);
> -}
> -- 
> 2.43.0
> 

[PATCH v2 02/10] target/microblaze: Introduce helper_unaligned_access

[Richard Henderson]

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/helper.h | 12 ++++++------
 target/microblaze/helper.c |  7 +++++++
 2 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h
index f740835fcb..41f56a5601 100644
--- a/target/microblaze/helper.h
+++ b/target/microblaze/helper.h
@@ -20,12 +20,12 @@ DEF_HELPER_FLAGS_3(fcmp_ne, TCG_CALL_NO_WG, i32, env, i32, i32)
 DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i32, i32)
 
 DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32)
-#if !defined(CONFIG_USER_ONLY)
-DEF_HELPER_FLAGS_3(mmu_read, TCG_CALL_NO_RWG, i32, env, i32, i32)
-DEF_HELPER_FLAGS_4(mmu_write, TCG_CALL_NO_RWG, void, env, i32, i32, i32)
-#endif
-
 DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl)
-
 DEF_HELPER_FLAGS_2(get, TCG_CALL_NO_RWG, i32, i32, i32)
 DEF_HELPER_FLAGS_3(put, TCG_CALL_NO_RWG, void, i32, i32, i32)
+
+#ifndef CONFIG_USER_ONLY
+DEF_HELPER_FLAGS_3(mmu_read, TCG_CALL_NO_RWG, i32, env, i32, i32)
+DEF_HELPER_FLAGS_4(mmu_write, TCG_CALL_NO_RWG, void, env, i32, i32, i32)
+DEF_HELPER_FLAGS_2(unaligned_access, TCG_CALL_NO_WG, noreturn, env, i64)
+#endif
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 5fe81e4b16..ef0e2f973f 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -26,6 +26,7 @@
 #include "exec/target_page.h"
 #include "qemu/host-utils.h"
 #include "exec/log.h"
+#include "exec/helper-proto.h"
 
 
 G_NORETURN
@@ -64,6 +65,12 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 }
 
 #ifndef CONFIG_USER_ONLY
+
+void HELPER(unaligned_access)(CPUMBState *env, uint64_t addr)
+{
+    mb_unaligned_access_internal(env_cpu(env), addr, GETPC());
+}
+
 static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu,
                                     MMUAccessType access_type)
 {
-- 
2.43.0

Re: [PATCH v2 02/10] target/microblaze: Introduce helper_unaligned_access

[Edgar E. Iglesias]

On Sun, May 25, 2025 at 05:02:12PM +0100, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>


> ---
>  target/microblaze/helper.h | 12 ++++++------
>  target/microblaze/helper.c |  7 +++++++
>  2 files changed, 13 insertions(+), 6 deletions(-)
> 
> diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h
> index f740835fcb..41f56a5601 100644
> --- a/target/microblaze/helper.h
> +++ b/target/microblaze/helper.h
> @@ -20,12 +20,12 @@ DEF_HELPER_FLAGS_3(fcmp_ne, TCG_CALL_NO_WG, i32, env, i32, i32)
>  DEF_HELPER_FLAGS_3(fcmp_ge, TCG_CALL_NO_WG, i32, env, i32, i32)
>  
>  DEF_HELPER_FLAGS_2(pcmpbf, TCG_CALL_NO_RWG_SE, i32, i32, i32)
> -#if !defined(CONFIG_USER_ONLY)
> -DEF_HELPER_FLAGS_3(mmu_read, TCG_CALL_NO_RWG, i32, env, i32, i32)
> -DEF_HELPER_FLAGS_4(mmu_write, TCG_CALL_NO_RWG, void, env, i32, i32, i32)
> -#endif
> -
>  DEF_HELPER_FLAGS_2(stackprot, TCG_CALL_NO_WG, void, env, tl)
> -
>  DEF_HELPER_FLAGS_2(get, TCG_CALL_NO_RWG, i32, i32, i32)
>  DEF_HELPER_FLAGS_3(put, TCG_CALL_NO_RWG, void, i32, i32, i32)
> +
> +#ifndef CONFIG_USER_ONLY
> +DEF_HELPER_FLAGS_3(mmu_read, TCG_CALL_NO_RWG, i32, env, i32, i32)
> +DEF_HELPER_FLAGS_4(mmu_write, TCG_CALL_NO_RWG, void, env, i32, i32, i32)
> +DEF_HELPER_FLAGS_2(unaligned_access, TCG_CALL_NO_WG, noreturn, env, i64)
> +#endif
> diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
> index 5fe81e4b16..ef0e2f973f 100644
> --- a/target/microblaze/helper.c
> +++ b/target/microblaze/helper.c
> @@ -26,6 +26,7 @@
>  #include "exec/target_page.h"
>  #include "qemu/host-utils.h"
>  #include "exec/log.h"
> +#include "exec/helper-proto.h"
>  
>  
>  G_NORETURN
> @@ -64,6 +65,12 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>  }
>  
>  #ifndef CONFIG_USER_ONLY
> +
> +void HELPER(unaligned_access)(CPUMBState *env, uint64_t addr)
> +{
> +    mb_unaligned_access_internal(env_cpu(env), addr, GETPC());
> +}
> +
>  static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu,
>                                      MMUAccessType access_type)
>  {
> -- 
> 2.43.0
> 

[PATCH v2 03/10] target/microblaze: Split out mb_transaction_failed_internal

[Richard Henderson]

Use an explicit 64-bit type for the address to store in EAR.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/op_helper.c | 70 +++++++++++++++++++++--------------
 1 file changed, 42 insertions(+), 28 deletions(-)

diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index 9e838dfa15..4c39207a55 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -393,38 +393,52 @@ void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v)
     mmu_write(env, ext, rn, v);
 }
 
+static void mb_transaction_failed_internal(CPUState *cs, hwaddr physaddr,
+                                           uint64_t addr, unsigned size,
+                                           MMUAccessType access_type,
+                                           uintptr_t retaddr)
+{
+    CPUMBState *env = cpu_env(cs);
+    MicroBlazeCPU *cpu = env_archcpu(env);
+    const char *access_name = "INVALID";
+    bool take = env->msr & MSR_EE;
+    uint32_t esr = ESR_EC_DATA_BUS;
+
+    switch (access_type) {
+    case MMU_INST_FETCH:
+        access_name = "INST_FETCH";
+        esr = ESR_EC_INSN_BUS;
+        take &= cpu->cfg.iopb_bus_exception;
+        break;
+    case MMU_DATA_LOAD:
+        access_name = "DATA_LOAD";
+        take &= cpu->cfg.dopb_bus_exception;
+        break;
+    case MMU_DATA_STORE:
+        access_name = "DATA_STORE";
+        take &= cpu->cfg.dopb_bus_exception;
+        break;
+    }
+
+    qemu_log_mask(CPU_LOG_INT, "Transaction failed: addr 0x%" PRIx64
+                  "physaddr 0x" HWADDR_FMT_plx " size %d access-type %s (%s)\n",
+                  addr, physaddr, size, access_name,
+                  take ? "TAKEN" : "DROPPED");
+
+    if (take) {
+        env->esr = esr;
+        env->ear = addr;
+        cs->exception_index = EXCP_HW_EXCP;
+        cpu_loop_exit_restore(cs, retaddr);
+    }
+}
+
 void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
                                unsigned size, MMUAccessType access_type,
                                int mmu_idx, MemTxAttrs attrs,
                                MemTxResult response, uintptr_t retaddr)
 {
-    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
-    CPUMBState *env = &cpu->env;
-
-    qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx
-                  " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n",
-                  addr, physaddr, size,
-                  access_type == MMU_INST_FETCH ? "INST_FETCH" :
-                  (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE"));
-
-    if (!(env->msr & MSR_EE)) {
-        return;
-    }
-
-    if (access_type == MMU_INST_FETCH) {
-        if (!cpu->cfg.iopb_bus_exception) {
-            return;
-        }
-        env->esr = ESR_EC_INSN_BUS;
-    } else {
-        if (!cpu->cfg.dopb_bus_exception) {
-            return;
-        }
-        env->esr = ESR_EC_DATA_BUS;
-    }
-
-    env->ear = addr;
-    cs->exception_index = EXCP_HW_EXCP;
-    cpu_loop_exit_restore(cs, retaddr);
+    mb_transaction_failed_internal(cs, physaddr, addr, size,
+                                   access_type, retaddr);
 }
 #endif
-- 
2.43.0

Re: [PATCH v2 03/10] target/microblaze: Split out mb_transaction_failed_internal

[Edgar E. Iglesias]

On Sun, May 25, 2025 at 05:02:13PM +0100, Richard Henderson wrote:
> Use an explicit 64-bit type for the address to store in EAR.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>


> ---
>  target/microblaze/op_helper.c | 70 +++++++++++++++++++++--------------
>  1 file changed, 42 insertions(+), 28 deletions(-)
> 
> diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
> index 9e838dfa15..4c39207a55 100644
> --- a/target/microblaze/op_helper.c
> +++ b/target/microblaze/op_helper.c
> @@ -393,38 +393,52 @@ void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v)
>      mmu_write(env, ext, rn, v);
>  }
>  
> +static void mb_transaction_failed_internal(CPUState *cs, hwaddr physaddr,
> +                                           uint64_t addr, unsigned size,
> +                                           MMUAccessType access_type,
> +                                           uintptr_t retaddr)
> +{
> +    CPUMBState *env = cpu_env(cs);
> +    MicroBlazeCPU *cpu = env_archcpu(env);
> +    const char *access_name = "INVALID";
> +    bool take = env->msr & MSR_EE;
> +    uint32_t esr = ESR_EC_DATA_BUS;
> +
> +    switch (access_type) {
> +    case MMU_INST_FETCH:
> +        access_name = "INST_FETCH";
> +        esr = ESR_EC_INSN_BUS;
> +        take &= cpu->cfg.iopb_bus_exception;
> +        break;
> +    case MMU_DATA_LOAD:
> +        access_name = "DATA_LOAD";
> +        take &= cpu->cfg.dopb_bus_exception;
> +        break;
> +    case MMU_DATA_STORE:
> +        access_name = "DATA_STORE";
> +        take &= cpu->cfg.dopb_bus_exception;
> +        break;
> +    }
> +
> +    qemu_log_mask(CPU_LOG_INT, "Transaction failed: addr 0x%" PRIx64
> +                  "physaddr 0x" HWADDR_FMT_plx " size %d access-type %s (%s)\n",
> +                  addr, physaddr, size, access_name,
> +                  take ? "TAKEN" : "DROPPED");
> +
> +    if (take) {
> +        env->esr = esr;
> +        env->ear = addr;
> +        cs->exception_index = EXCP_HW_EXCP;
> +        cpu_loop_exit_restore(cs, retaddr);
> +    }
> +}
> +
>  void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
>                                 unsigned size, MMUAccessType access_type,
>                                 int mmu_idx, MemTxAttrs attrs,
>                                 MemTxResult response, uintptr_t retaddr)
>  {
> -    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> -    CPUMBState *env = &cpu->env;
> -
> -    qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx
> -                  " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n",
> -                  addr, physaddr, size,
> -                  access_type == MMU_INST_FETCH ? "INST_FETCH" :
> -                  (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE"));
> -
> -    if (!(env->msr & MSR_EE)) {
> -        return;
> -    }
> -
> -    if (access_type == MMU_INST_FETCH) {
> -        if (!cpu->cfg.iopb_bus_exception) {
> -            return;
> -        }
> -        env->esr = ESR_EC_INSN_BUS;
> -    } else {
> -        if (!cpu->cfg.dopb_bus_exception) {
> -            return;
> -        }
> -        env->esr = ESR_EC_DATA_BUS;
> -    }
> -
> -    env->ear = addr;
> -    cs->exception_index = EXCP_HW_EXCP;
> -    cpu_loop_exit_restore(cs, retaddr);
> +    mb_transaction_failed_internal(cs, physaddr, addr, size,
> +                                   access_type, retaddr);
>  }
>  #endif
> -- 
> 2.43.0
> 

[PATCH v2 04/10] target/microblaze: Implement extended address load/store out of line

[Richard Henderson]

Use helpers and address_space_ld/st instead of inline
loads and stores.  This allows us to perform operations
on physical addresses wider than virtual addresses.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/helper.h    | 10 +++++++
 target/microblaze/op_helper.c | 40 +++++++++++++++++++++++++++
 target/microblaze/translate.c | 52 +++++++++++++++++++++++++++--------
 3 files changed, 90 insertions(+), 12 deletions(-)

diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h
index 41f56a5601..ef4fad9b91 100644
--- a/target/microblaze/helper.h
+++ b/target/microblaze/helper.h
@@ -28,4 +28,14 @@ DEF_HELPER_FLAGS_3(put, TCG_CALL_NO_RWG, void, i32, i32, i32)
 DEF_HELPER_FLAGS_3(mmu_read, TCG_CALL_NO_RWG, i32, env, i32, i32)
 DEF_HELPER_FLAGS_4(mmu_write, TCG_CALL_NO_RWG, void, env, i32, i32, i32)
 DEF_HELPER_FLAGS_2(unaligned_access, TCG_CALL_NO_WG, noreturn, env, i64)
+DEF_HELPER_FLAGS_2(lbuea, TCG_CALL_NO_WG, i32, env, i64)
+DEF_HELPER_FLAGS_2(lhuea_be, TCG_CALL_NO_WG, i32, env, i64)
+DEF_HELPER_FLAGS_2(lhuea_le, TCG_CALL_NO_WG, i32, env, i64)
+DEF_HELPER_FLAGS_2(lwea_be, TCG_CALL_NO_WG, i32, env, i64)
+DEF_HELPER_FLAGS_2(lwea_le, TCG_CALL_NO_WG, i32, env, i64)
+DEF_HELPER_FLAGS_3(sbea, TCG_CALL_NO_WG, void, env, i32, i64)
+DEF_HELPER_FLAGS_3(shea_be, TCG_CALL_NO_WG, void, env, i32, i64)
+DEF_HELPER_FLAGS_3(shea_le, TCG_CALL_NO_WG, void, env, i32, i64)
+DEF_HELPER_FLAGS_3(swea_be, TCG_CALL_NO_WG, void, env, i32, i64)
+DEF_HELPER_FLAGS_3(swea_le, TCG_CALL_NO_WG, void, env, i32, i64)
 #endif
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index 4c39207a55..b8365b3b1d 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -382,6 +382,8 @@ void helper_stackprot(CPUMBState *env, target_ulong addr)
 }
 
 #if !defined(CONFIG_USER_ONLY)
+#include "system/memory.h"
+
 /* Writes/reads to the MMU's special regs end up here.  */
 uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
 {
@@ -441,4 +443,42 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
     mb_transaction_failed_internal(cs, physaddr, addr, size,
                                    access_type, retaddr);
 }
+
+#define LD_EA(NAME, TYPE, FUNC) \
+uint32_t HELPER(NAME)(CPUMBState *env, uint64_t ea)                     \
+{                                                                       \
+    CPUState *cs = env_cpu(env);                                        \
+    MemTxResult txres;                                                  \
+    TYPE ret = FUNC(cs->as, ea, MEMTXATTRS_UNSPECIFIED, &txres);        \
+    if (unlikely(txres != MEMTX_OK)) {                                  \
+        mb_transaction_failed_internal(cs, ea, ea, sizeof(TYPE),        \
+                                       MMU_DATA_LOAD, GETPC());         \
+    }                                                                   \
+    return ret;                                                         \
+}
+
+LD_EA(lbuea, uint8_t, address_space_ldub)
+LD_EA(lhuea_be, uint16_t, address_space_lduw_be)
+LD_EA(lhuea_le, uint16_t, address_space_lduw_le)
+LD_EA(lwea_be, uint32_t, address_space_ldl_be)
+LD_EA(lwea_le, uint32_t, address_space_ldl_le)
+
+#define ST_EA(NAME, TYPE, FUNC) \
+void HELPER(NAME)(CPUMBState *env, uint32_t data, uint64_t ea)          \
+{                                                                       \
+    CPUState *cs = env_cpu(env);                                        \
+    MemTxResult txres;                                                  \
+    FUNC(cs->as, ea, data, MEMTXATTRS_UNSPECIFIED, &txres);             \
+    if (unlikely(txres != MEMTX_OK)) {                                  \
+        mb_transaction_failed_internal(cs, ea, ea, sizeof(TYPE),        \
+                                       MMU_DATA_STORE, GETPC());        \
+    }                                                                   \
+}
+
+ST_EA(sbea, uint8_t, address_space_stb)
+ST_EA(shea_be, uint16_t, address_space_stw_be)
+ST_EA(shea_le, uint16_t, address_space_stw_le)
+ST_EA(swea_be, uint32_t, address_space_stl_be)
+ST_EA(swea_le, uint32_t, address_space_stl_le)
+
 #endif
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 671b1ae4db..3d9756391e 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -700,6 +700,20 @@ static void record_unaligned_ess(DisasContext *dc, int rd,
 
     tcg_set_insn_start_param(dc->base.insn_start, 1, iflags);
 }
+
+static void gen_alignment_check_ea(DisasContext *dc, TCGv_i64 ea, int rb,
+                                   int rd, MemOp size, bool store)
+{
+    if (rb && (dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) {
+        TCGLabel *over = gen_new_label();
+
+        record_unaligned_ess(dc, rd, size, store);
+
+        tcg_gen_brcondi_i64(TCG_COND_TSTEQ, ea, (1 << size) - 1, over);
+        gen_helper_unaligned_access(tcg_env, ea);
+        gen_set_label(over);
+    }
+}
 #endif
 
 static inline MemOp mo_endian(DisasContext *dc)
@@ -765,10 +779,11 @@ static bool trans_lbuea(DisasContext *dc, arg_typea *arg)
         return true;
     }
 #ifdef CONFIG_USER_ONLY
-    return true;
+    g_assert_not_reached();
 #else
     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
-    return do_load(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false);
+    gen_helper_lbuea(reg_for_write(dc, arg->rd), tcg_env, addr);
+    return true;
 #endif
 }
 
@@ -796,10 +811,13 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
         return true;
     }
 #ifdef CONFIG_USER_ONLY
-    return true;
+    g_assert_not_reached();
 #else
     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
-    return do_load(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false);
+    gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_16, false);
+    (mo_endian(dc) == MO_BE ? gen_helper_lhuea_be : gen_helper_lhuea_le)
+        (reg_for_write(dc, arg->rd), tcg_env, addr);
+    return true;
 #endif
 }
 
@@ -827,10 +845,13 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
         return true;
     }
 #ifdef CONFIG_USER_ONLY
-    return true;
+    g_assert_not_reached();
 #else
     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
-    return do_load(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false);
+    gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_32, false);
+    (mo_endian(dc) == MO_BE ? gen_helper_lwea_be : gen_helper_lwea_le)
+        (reg_for_write(dc, arg->rd), tcg_env, addr);
+    return true;
 #endif
 }
 
@@ -918,10 +939,11 @@ static bool trans_sbea(DisasContext *dc, arg_typea *arg)
         return true;
     }
 #ifdef CONFIG_USER_ONLY
-    return true;
+    g_assert_not_reached();
 #else
     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
-    return do_store(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false);
+    gen_helper_sbea(tcg_env, reg_for_read(dc, arg->rd), addr);
+    return true;
 #endif
 }
 
@@ -949,10 +971,13 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
         return true;
     }
 #ifdef CONFIG_USER_ONLY
-    return true;
+    g_assert_not_reached();
 #else
     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
-    return do_store(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false);
+    gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_16, true);
+    (mo_endian(dc) == MO_BE ? gen_helper_shea_be : gen_helper_shea_le)
+        (tcg_env, reg_for_read(dc, arg->rd), addr);
+    return true;
 #endif
 }
 
@@ -980,10 +1005,13 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
         return true;
     }
 #ifdef CONFIG_USER_ONLY
-    return true;
+    g_assert_not_reached();
 #else
     TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
-    return do_store(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false);
+    gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_32, true);
+    (mo_endian(dc) == MO_BE ? gen_helper_swea_be : gen_helper_swea_le)
+        (tcg_env, reg_for_read(dc, arg->rd), addr);
+    return true;
 #endif
 }
 
-- 
2.43.0

Re: [PATCH v2 04/10] target/microblaze: Implement extended address load/store out of line

[Edgar E. Iglesias]

On Sun, May 25, 2025 at 05:02:14PM +0100, Richard Henderson wrote:
> Use helpers and address_space_ld/st instead of inline
> loads and stores.  This allows us to perform operations
> on physical addresses wider than virtual addresses.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>


> ---
>  target/microblaze/helper.h    | 10 +++++++
>  target/microblaze/op_helper.c | 40 +++++++++++++++++++++++++++
>  target/microblaze/translate.c | 52 +++++++++++++++++++++++++++--------
>  3 files changed, 90 insertions(+), 12 deletions(-)
> 
> diff --git a/target/microblaze/helper.h b/target/microblaze/helper.h
> index 41f56a5601..ef4fad9b91 100644
> --- a/target/microblaze/helper.h
> +++ b/target/microblaze/helper.h
> @@ -28,4 +28,14 @@ DEF_HELPER_FLAGS_3(put, TCG_CALL_NO_RWG, void, i32, i32, i32)
>  DEF_HELPER_FLAGS_3(mmu_read, TCG_CALL_NO_RWG, i32, env, i32, i32)
>  DEF_HELPER_FLAGS_4(mmu_write, TCG_CALL_NO_RWG, void, env, i32, i32, i32)
>  DEF_HELPER_FLAGS_2(unaligned_access, TCG_CALL_NO_WG, noreturn, env, i64)
> +DEF_HELPER_FLAGS_2(lbuea, TCG_CALL_NO_WG, i32, env, i64)
> +DEF_HELPER_FLAGS_2(lhuea_be, TCG_CALL_NO_WG, i32, env, i64)
> +DEF_HELPER_FLAGS_2(lhuea_le, TCG_CALL_NO_WG, i32, env, i64)
> +DEF_HELPER_FLAGS_2(lwea_be, TCG_CALL_NO_WG, i32, env, i64)
> +DEF_HELPER_FLAGS_2(lwea_le, TCG_CALL_NO_WG, i32, env, i64)
> +DEF_HELPER_FLAGS_3(sbea, TCG_CALL_NO_WG, void, env, i32, i64)
> +DEF_HELPER_FLAGS_3(shea_be, TCG_CALL_NO_WG, void, env, i32, i64)
> +DEF_HELPER_FLAGS_3(shea_le, TCG_CALL_NO_WG, void, env, i32, i64)
> +DEF_HELPER_FLAGS_3(swea_be, TCG_CALL_NO_WG, void, env, i32, i64)
> +DEF_HELPER_FLAGS_3(swea_le, TCG_CALL_NO_WG, void, env, i32, i64)
>  #endif
> diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
> index 4c39207a55..b8365b3b1d 100644
> --- a/target/microblaze/op_helper.c
> +++ b/target/microblaze/op_helper.c
> @@ -382,6 +382,8 @@ void helper_stackprot(CPUMBState *env, target_ulong addr)
>  }
>  
>  #if !defined(CONFIG_USER_ONLY)
> +#include "system/memory.h"
> +
>  /* Writes/reads to the MMU's special regs end up here.  */
>  uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
>  {
> @@ -441,4 +443,42 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
>      mb_transaction_failed_internal(cs, physaddr, addr, size,
>                                     access_type, retaddr);
>  }
> +
> +#define LD_EA(NAME, TYPE, FUNC) \
> +uint32_t HELPER(NAME)(CPUMBState *env, uint64_t ea)                     \
> +{                                                                       \
> +    CPUState *cs = env_cpu(env);                                        \
> +    MemTxResult txres;                                                  \
> +    TYPE ret = FUNC(cs->as, ea, MEMTXATTRS_UNSPECIFIED, &txres);        \
> +    if (unlikely(txres != MEMTX_OK)) {                                  \
> +        mb_transaction_failed_internal(cs, ea, ea, sizeof(TYPE),        \
> +                                       MMU_DATA_LOAD, GETPC());         \
> +    }                                                                   \
> +    return ret;                                                         \
> +}
> +
> +LD_EA(lbuea, uint8_t, address_space_ldub)
> +LD_EA(lhuea_be, uint16_t, address_space_lduw_be)
> +LD_EA(lhuea_le, uint16_t, address_space_lduw_le)
> +LD_EA(lwea_be, uint32_t, address_space_ldl_be)
> +LD_EA(lwea_le, uint32_t, address_space_ldl_le)
> +
> +#define ST_EA(NAME, TYPE, FUNC) \
> +void HELPER(NAME)(CPUMBState *env, uint32_t data, uint64_t ea)          \
> +{                                                                       \
> +    CPUState *cs = env_cpu(env);                                        \
> +    MemTxResult txres;                                                  \
> +    FUNC(cs->as, ea, data, MEMTXATTRS_UNSPECIFIED, &txres);             \
> +    if (unlikely(txres != MEMTX_OK)) {                                  \
> +        mb_transaction_failed_internal(cs, ea, ea, sizeof(TYPE),        \
> +                                       MMU_DATA_STORE, GETPC());        \
> +    }                                                                   \
> +}
> +
> +ST_EA(sbea, uint8_t, address_space_stb)
> +ST_EA(shea_be, uint16_t, address_space_stw_be)
> +ST_EA(shea_le, uint16_t, address_space_stw_le)
> +ST_EA(swea_be, uint32_t, address_space_stl_be)
> +ST_EA(swea_le, uint32_t, address_space_stl_le)
> +
>  #endif
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 671b1ae4db..3d9756391e 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -700,6 +700,20 @@ static void record_unaligned_ess(DisasContext *dc, int rd,
>  
>      tcg_set_insn_start_param(dc->base.insn_start, 1, iflags);
>  }
> +
> +static void gen_alignment_check_ea(DisasContext *dc, TCGv_i64 ea, int rb,
> +                                   int rd, MemOp size, bool store)
> +{
> +    if (rb && (dc->tb_flags & MSR_EE) && dc->cfg->unaligned_exceptions) {
> +        TCGLabel *over = gen_new_label();
> +
> +        record_unaligned_ess(dc, rd, size, store);
> +
> +        tcg_gen_brcondi_i64(TCG_COND_TSTEQ, ea, (1 << size) - 1, over);
> +        gen_helper_unaligned_access(tcg_env, ea);
> +        gen_set_label(over);
> +    }
> +}
>  #endif
>  
>  static inline MemOp mo_endian(DisasContext *dc)
> @@ -765,10 +779,11 @@ static bool trans_lbuea(DisasContext *dc, arg_typea *arg)
>          return true;
>      }
>  #ifdef CONFIG_USER_ONLY
> -    return true;
> +    g_assert_not_reached();
>  #else
>      TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
> -    return do_load(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false);
> +    gen_helper_lbuea(reg_for_write(dc, arg->rd), tcg_env, addr);
> +    return true;
>  #endif
>  }
>  
> @@ -796,10 +811,13 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
>          return true;
>      }
>  #ifdef CONFIG_USER_ONLY
> -    return true;
> +    g_assert_not_reached();
>  #else
>      TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
> -    return do_load(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false);
> +    gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_16, false);
> +    (mo_endian(dc) == MO_BE ? gen_helper_lhuea_be : gen_helper_lhuea_le)
> +        (reg_for_write(dc, arg->rd), tcg_env, addr);
> +    return true;
>  #endif
>  }
>  
> @@ -827,10 +845,13 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
>          return true;
>      }
>  #ifdef CONFIG_USER_ONLY
> -    return true;
> +    g_assert_not_reached();
>  #else
>      TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
> -    return do_load(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false);
> +    gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_32, false);
> +    (mo_endian(dc) == MO_BE ? gen_helper_lwea_be : gen_helper_lwea_le)
> +        (reg_for_write(dc, arg->rd), tcg_env, addr);
> +    return true;
>  #endif
>  }
>  
> @@ -918,10 +939,11 @@ static bool trans_sbea(DisasContext *dc, arg_typea *arg)
>          return true;
>      }
>  #ifdef CONFIG_USER_ONLY
> -    return true;
> +    g_assert_not_reached();
>  #else
>      TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
> -    return do_store(dc, arg->rd, addr, MO_UB, MMU_NOMMU_IDX, false);
> +    gen_helper_sbea(tcg_env, reg_for_read(dc, arg->rd), addr);
> +    return true;
>  #endif
>  }
>  
> @@ -949,10 +971,13 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
>          return true;
>      }
>  #ifdef CONFIG_USER_ONLY
> -    return true;
> +    g_assert_not_reached();
>  #else
>      TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
> -    return do_store(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false);
> +    gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_16, true);
> +    (mo_endian(dc) == MO_BE ? gen_helper_shea_be : gen_helper_shea_le)
> +        (tcg_env, reg_for_read(dc, arg->rd), addr);
> +    return true;
>  #endif
>  }
>  
> @@ -980,10 +1005,13 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
>          return true;
>      }
>  #ifdef CONFIG_USER_ONLY
> -    return true;
> +    g_assert_not_reached();
>  #else
>      TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
> -    return do_store(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false);
> +    gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_32, true);
> +    (mo_endian(dc) == MO_BE ? gen_helper_swea_be : gen_helper_swea_le)
> +        (tcg_env, reg_for_read(dc, arg->rd), addr);
> +    return true;
>  #endif
>  }
>  
> -- 
> 2.43.0
> 

[PATCH v2 05/10] target/microblaze: Use uint64_t for CPUMBState.ear

[Richard Henderson]

Use an explicit 64-bit type for EAR.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/cpu.h       | 2 +-
 target/microblaze/translate.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 6ad8643f2e..3ce28b302f 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -248,7 +248,7 @@ struct CPUArchState {
     uint32_t pc;
     uint32_t msr;    /* All bits of MSR except MSR[C] and MSR[CC] */
     uint32_t msr_c;  /* MSR[C], in low bit; other bits must be 0 */
-    target_ulong ear;
+    uint64_t ear;
     uint32_t esr;
     uint32_t fsr;
     uint32_t btr;
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 3d9756391e..b1fc9e5624 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1857,7 +1857,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     }
 
     qemu_fprintf(f, "\nesr=0x%04x fsr=0x%02x btr=0x%08x edr=0x%x\n"
-                 "ear=0x" TARGET_FMT_lx " slr=0x%x shr=0x%x\n",
+                 "ear=0x%" PRIx64 " slr=0x%x shr=0x%x\n",
                  env->esr, env->fsr, env->btr, env->edr,
                  env->ear, env->slr, env->shr);
 
-- 
2.43.0

Re: [PATCH v2 05/10] target/microblaze: Use uint64_t for CPUMBState.ear

[Edgar E. Iglesias]

On Sun, May 25, 2025 at 05:02:15PM +0100, Richard Henderson wrote:
> Use an explicit 64-bit type for EAR.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>


> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/microblaze/cpu.h       | 2 +-
>  target/microblaze/translate.c | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 6ad8643f2e..3ce28b302f 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -248,7 +248,7 @@ struct CPUArchState {
>      uint32_t pc;
>      uint32_t msr;    /* All bits of MSR except MSR[C] and MSR[CC] */
>      uint32_t msr_c;  /* MSR[C], in low bit; other bits must be 0 */
> -    target_ulong ear;
> +    uint64_t ear;
>      uint32_t esr;
>      uint32_t fsr;
>      uint32_t btr;
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 3d9756391e..b1fc9e5624 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -1857,7 +1857,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>      }
>  
>      qemu_fprintf(f, "\nesr=0x%04x fsr=0x%02x btr=0x%08x edr=0x%x\n"
> -                 "ear=0x" TARGET_FMT_lx " slr=0x%x shr=0x%x\n",
> +                 "ear=0x%" PRIx64 " slr=0x%x shr=0x%x\n",
>                   env->esr, env->fsr, env->btr, env->edr,
>                   env->ear, env->slr, env->shr);
>  
> -- 
> 2.43.0
> 

[PATCH v2 06/10] target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea

[Richard Henderson]

Use an explicit 64-bit type for extended addresses.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/translate.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index b1fc9e5624..dc597b36e6 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -660,23 +660,23 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm)
 }
 
 #ifndef CONFIG_USER_ONLY
-static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb)
+static TCGv_i64 compute_ldst_addr_ea(DisasContext *dc, int ra, int rb)
 {
     int addr_size = dc->cfg->addr_size;
-    TCGv ret = tcg_temp_new();
+    TCGv_i64 ret = tcg_temp_new_i64();
 
     if (addr_size == 32 || ra == 0) {
         if (rb) {
-            tcg_gen_extu_i32_tl(ret, cpu_R[rb]);
+            tcg_gen_extu_i32_i64(ret, cpu_R[rb]);
         } else {
-            tcg_gen_movi_tl(ret, 0);
+            return tcg_constant_i64(0);
         }
     } else {
         if (rb) {
             tcg_gen_concat_i32_i64(ret, cpu_R[rb], cpu_R[ra]);
         } else {
-            tcg_gen_extu_i32_tl(ret, cpu_R[ra]);
-            tcg_gen_shli_tl(ret, ret, 32);
+            tcg_gen_extu_i32_i64(ret, cpu_R[ra]);
+            tcg_gen_shli_i64(ret, ret, 32);
         }
         if (addr_size < 64) {
             /* Mask off out of range bits.  */
@@ -781,7 +781,7 @@ static bool trans_lbuea(DisasContext *dc, arg_typea *arg)
 #ifdef CONFIG_USER_ONLY
     g_assert_not_reached();
 #else
-    TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
+    TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
     gen_helper_lbuea(reg_for_write(dc, arg->rd), tcg_env, addr);
     return true;
 #endif
@@ -813,7 +813,7 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
 #ifdef CONFIG_USER_ONLY
     g_assert_not_reached();
 #else
-    TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
+    TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
     gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_16, false);
     (mo_endian(dc) == MO_BE ? gen_helper_lhuea_be : gen_helper_lhuea_le)
         (reg_for_write(dc, arg->rd), tcg_env, addr);
@@ -847,7 +847,7 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
 #ifdef CONFIG_USER_ONLY
     g_assert_not_reached();
 #else
-    TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
+    TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
     gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_32, false);
     (mo_endian(dc) == MO_BE ? gen_helper_lwea_be : gen_helper_lwea_le)
         (reg_for_write(dc, arg->rd), tcg_env, addr);
@@ -941,7 +941,7 @@ static bool trans_sbea(DisasContext *dc, arg_typea *arg)
 #ifdef CONFIG_USER_ONLY
     g_assert_not_reached();
 #else
-    TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
+    TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
     gen_helper_sbea(tcg_env, reg_for_read(dc, arg->rd), addr);
     return true;
 #endif
@@ -973,7 +973,7 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
 #ifdef CONFIG_USER_ONLY
     g_assert_not_reached();
 #else
-    TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
+    TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
     gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_16, true);
     (mo_endian(dc) == MO_BE ? gen_helper_shea_be : gen_helper_shea_le)
         (tcg_env, reg_for_read(dc, arg->rd), addr);
@@ -1007,7 +1007,7 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
 #ifdef CONFIG_USER_ONLY
     g_assert_not_reached();
 #else
-    TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
+    TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
     gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_32, true);
     (mo_endian(dc) == MO_BE ? gen_helper_swea_be : gen_helper_swea_le)
         (tcg_env, reg_for_read(dc, arg->rd), addr);
-- 
2.43.0

Re: [PATCH v2 06/10] target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea

[Edgar E. Iglesias]

On Sun, May 25, 2025 at 05:02:16PM +0100, Richard Henderson wrote:
> Use an explicit 64-bit type for extended addresses.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>


> ---
>  target/microblaze/translate.c | 24 ++++++++++++------------
>  1 file changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index b1fc9e5624..dc597b36e6 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -660,23 +660,23 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm)
>  }
>  
>  #ifndef CONFIG_USER_ONLY
> -static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb)
> +static TCGv_i64 compute_ldst_addr_ea(DisasContext *dc, int ra, int rb)
>  {
>      int addr_size = dc->cfg->addr_size;
> -    TCGv ret = tcg_temp_new();
> +    TCGv_i64 ret = tcg_temp_new_i64();
>  
>      if (addr_size == 32 || ra == 0) {
>          if (rb) {
> -            tcg_gen_extu_i32_tl(ret, cpu_R[rb]);
> +            tcg_gen_extu_i32_i64(ret, cpu_R[rb]);
>          } else {
> -            tcg_gen_movi_tl(ret, 0);
> +            return tcg_constant_i64(0);
>          }
>      } else {
>          if (rb) {
>              tcg_gen_concat_i32_i64(ret, cpu_R[rb], cpu_R[ra]);
>          } else {
> -            tcg_gen_extu_i32_tl(ret, cpu_R[ra]);
> -            tcg_gen_shli_tl(ret, ret, 32);
> +            tcg_gen_extu_i32_i64(ret, cpu_R[ra]);
> +            tcg_gen_shli_i64(ret, ret, 32);
>          }
>          if (addr_size < 64) {
>              /* Mask off out of range bits.  */
> @@ -781,7 +781,7 @@ static bool trans_lbuea(DisasContext *dc, arg_typea *arg)
>  #ifdef CONFIG_USER_ONLY
>      g_assert_not_reached();
>  #else
> -    TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
> +    TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
>      gen_helper_lbuea(reg_for_write(dc, arg->rd), tcg_env, addr);
>      return true;
>  #endif
> @@ -813,7 +813,7 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
>  #ifdef CONFIG_USER_ONLY
>      g_assert_not_reached();
>  #else
> -    TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
> +    TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
>      gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_16, false);
>      (mo_endian(dc) == MO_BE ? gen_helper_lhuea_be : gen_helper_lhuea_le)
>          (reg_for_write(dc, arg->rd), tcg_env, addr);
> @@ -847,7 +847,7 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
>  #ifdef CONFIG_USER_ONLY
>      g_assert_not_reached();
>  #else
> -    TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
> +    TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
>      gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_32, false);
>      (mo_endian(dc) == MO_BE ? gen_helper_lwea_be : gen_helper_lwea_le)
>          (reg_for_write(dc, arg->rd), tcg_env, addr);
> @@ -941,7 +941,7 @@ static bool trans_sbea(DisasContext *dc, arg_typea *arg)
>  #ifdef CONFIG_USER_ONLY
>      g_assert_not_reached();
>  #else
> -    TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
> +    TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
>      gen_helper_sbea(tcg_env, reg_for_read(dc, arg->rd), addr);
>      return true;
>  #endif
> @@ -973,7 +973,7 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
>  #ifdef CONFIG_USER_ONLY
>      g_assert_not_reached();
>  #else
> -    TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
> +    TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
>      gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_16, true);
>      (mo_endian(dc) == MO_BE ? gen_helper_shea_be : gen_helper_shea_le)
>          (tcg_env, reg_for_read(dc, arg->rd), addr);
> @@ -1007,7 +1007,7 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
>  #ifdef CONFIG_USER_ONLY
>      g_assert_not_reached();
>  #else
> -    TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
> +    TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
>      gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_32, true);
>      (mo_endian(dc) == MO_BE ? gen_helper_swea_be : gen_helper_swea_le)
>          (tcg_env, reg_for_read(dc, arg->rd), addr);
> -- 
> 2.43.0
> 

[PATCH v2 07/10] target/microblaze: Fix printf format in mmu_translate

[Richard Henderson]

Use TARGET_FMT_lx to match the target_ulong type of vaddr.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/mmu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 95a12e16f8..8703ff5c65 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -172,7 +172,8 @@ unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
     }
 done:
     qemu_log_mask(CPU_LOG_MMU,
-                  "MMU vaddr=%" PRIx64 " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
+                  "MMU vaddr=0x" TARGET_FMT_lx
+                  " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
                   vaddr, rw, tlb_wr, tlb_ex, hit);
     return hit;
 }
-- 
2.43.0

Re: [PATCH v2 07/10] target/microblaze: Fix printf format in mmu_translate

[Edgar E. Iglesias]

On Sun, May 25, 2025 at 05:02:17PM +0100, Richard Henderson wrote:
> Use TARGET_FMT_lx to match the target_ulong type of vaddr.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>


> ---
>  target/microblaze/mmu.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
> index 95a12e16f8..8703ff5c65 100644
> --- a/target/microblaze/mmu.c
> +++ b/target/microblaze/mmu.c
> @@ -172,7 +172,8 @@ unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
>      }
>  done:
>      qemu_log_mask(CPU_LOG_MMU,
> -                  "MMU vaddr=%" PRIx64 " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
> +                  "MMU vaddr=0x" TARGET_FMT_lx
> +                  " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
>                    vaddr, rw, tlb_wr, tlb_ex, hit);
>      return hit;
>  }
> -- 
> 2.43.0
> 

[PATCH v2 08/10] target/microblaze: Use TARGET_LONG_BITS == 32 for system mode

[Richard Henderson]

Now that the extended address instructions are handled separately
from virtual addresses, we can narrow the emulation to 32-bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 configs/targets/microblaze-softmmu.mak   | 4 +---
 configs/targets/microblazeel-softmmu.mak | 4 +---
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/configs/targets/microblaze-softmmu.mak b/configs/targets/microblaze-softmmu.mak
index 23457d0ae6..bab7b498c2 100644
--- a/configs/targets/microblaze-softmmu.mak
+++ b/configs/targets/microblaze-softmmu.mak
@@ -3,6 +3,4 @@ TARGET_BIG_ENDIAN=y
 # needed by boot.c
 TARGET_NEED_FDT=y
 TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml
-# System mode can address up to 64 bits via lea/sea instructions.
-# TODO: These bypass the mmu, so we could emulate these differently.
-TARGET_LONG_BITS=64
+TARGET_LONG_BITS=32
diff --git a/configs/targets/microblazeel-softmmu.mak b/configs/targets/microblazeel-softmmu.mak
index c82c509623..8aee7ebc5c 100644
--- a/configs/targets/microblazeel-softmmu.mak
+++ b/configs/targets/microblazeel-softmmu.mak
@@ -2,6 +2,4 @@ TARGET_ARCH=microblaze
 # needed by boot.c
 TARGET_NEED_FDT=y
 TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml
-# System mode can address up to 64 bits via lea/sea instructions.
-# TODO: These bypass the mmu, so we could emulate these differently.
-TARGET_LONG_BITS=64
+TARGET_LONG_BITS=32
-- 
2.43.0

Re: [PATCH v2 08/10] target/microblaze: Use TARGET_LONG_BITS == 32 for system mode

[Edgar E. Iglesias]

On Sun, May 25, 2025 at 05:02:18PM +0100, Richard Henderson wrote:
> Now that the extended address instructions are handled separately
> from virtual addresses, we can narrow the emulation to 32-bit.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>


> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  configs/targets/microblaze-softmmu.mak   | 4 +---
>  configs/targets/microblazeel-softmmu.mak | 4 +---
>  2 files changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/configs/targets/microblaze-softmmu.mak b/configs/targets/microblaze-softmmu.mak
> index 23457d0ae6..bab7b498c2 100644
> --- a/configs/targets/microblaze-softmmu.mak
> +++ b/configs/targets/microblaze-softmmu.mak
> @@ -3,6 +3,4 @@ TARGET_BIG_ENDIAN=y
>  # needed by boot.c
>  TARGET_NEED_FDT=y
>  TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml
> -# System mode can address up to 64 bits via lea/sea instructions.
> -# TODO: These bypass the mmu, so we could emulate these differently.
> -TARGET_LONG_BITS=64
> +TARGET_LONG_BITS=32
> diff --git a/configs/targets/microblazeel-softmmu.mak b/configs/targets/microblazeel-softmmu.mak
> index c82c509623..8aee7ebc5c 100644
> --- a/configs/targets/microblazeel-softmmu.mak
> +++ b/configs/targets/microblazeel-softmmu.mak
> @@ -2,6 +2,4 @@ TARGET_ARCH=microblaze
>  # needed by boot.c
>  TARGET_NEED_FDT=y
>  TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml
> -# System mode can address up to 64 bits via lea/sea instructions.
> -# TODO: These bypass the mmu, so we could emulate these differently.
> -TARGET_LONG_BITS=64
> +TARGET_LONG_BITS=32
> -- 
> 2.43.0
> 

[PATCH v2 09/10] target/microblaze: Drop DisasContext.r0

[Richard Henderson]

Return a constant 0 from reg_for_read, and a new
temporary from reg_for_write.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/translate.c | 24 ++----------------------
 1 file changed, 2 insertions(+), 22 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index dc597b36e6..047d97e2c5 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -63,9 +63,6 @@ typedef struct DisasContext {
     DisasContextBase base;
     const MicroBlazeCPUConfig *cfg;
 
-    TCGv_i32 r0;
-    bool r0_set;
-
     /* Decoder.  */
     uint32_t ext_imm;
     unsigned int tb_flags;
@@ -179,14 +176,7 @@ static TCGv_i32 reg_for_read(DisasContext *dc, int reg)
     if (likely(reg != 0)) {
         return cpu_R[reg];
     }
-    if (!dc->r0_set) {
-        if (dc->r0 == NULL) {
-            dc->r0 = tcg_temp_new_i32();
-        }
-        tcg_gen_movi_i32(dc->r0, 0);
-        dc->r0_set = true;
-    }
-    return dc->r0;
+    return tcg_constant_i32(0);
 }
 
 static TCGv_i32 reg_for_write(DisasContext *dc, int reg)
@@ -194,10 +184,7 @@ static TCGv_i32 reg_for_write(DisasContext *dc, int reg)
     if (likely(reg != 0)) {
         return cpu_R[reg];
     }
-    if (dc->r0 == NULL) {
-        dc->r0 = tcg_temp_new_i32();
-    }
-    return dc->r0;
+    return tcg_temp_new_i32();
 }
 
 static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects,
@@ -1635,8 +1622,6 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
     dc->cfg = &cpu->cfg;
     dc->tb_flags = dc->base.tb->flags;
     dc->ext_imm = dc->base.tb->cs_base;
-    dc->r0 = NULL;
-    dc->r0_set = false;
     dc->mem_index = cpu_mmu_index(cs, false);
     dc->jmp_cond = dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NEVER;
     dc->jmp_dest = -1;
@@ -1675,11 +1660,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
         trap_illegal(dc, true);
     }
 
-    if (dc->r0) {
-        dc->r0 = NULL;
-        dc->r0_set = false;
-    }
-
     /* Discard the imm global when its contents cannot be used. */
     if ((dc->tb_flags & ~dc->tb_flags_to_set) & IMM_FLAG) {
         tcg_gen_discard_i32(cpu_imm);
-- 
2.43.0

Re: [PATCH v2 09/10] target/microblaze: Drop DisasContext.r0

[Edgar E. Iglesias]

On Sun, May 25, 2025 at 05:02:19PM +0100, Richard Henderson wrote:
> Return a constant 0 from reg_for_read, and a new
> temporary from reg_for_write.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>



> ---
>  target/microblaze/translate.c | 24 ++----------------------
>  1 file changed, 2 insertions(+), 22 deletions(-)
> 
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index dc597b36e6..047d97e2c5 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -63,9 +63,6 @@ typedef struct DisasContext {
>      DisasContextBase base;
>      const MicroBlazeCPUConfig *cfg;
>  
> -    TCGv_i32 r0;
> -    bool r0_set;
> -
>      /* Decoder.  */
>      uint32_t ext_imm;
>      unsigned int tb_flags;
> @@ -179,14 +176,7 @@ static TCGv_i32 reg_for_read(DisasContext *dc, int reg)
>      if (likely(reg != 0)) {
>          return cpu_R[reg];
>      }
> -    if (!dc->r0_set) {
> -        if (dc->r0 == NULL) {
> -            dc->r0 = tcg_temp_new_i32();
> -        }
> -        tcg_gen_movi_i32(dc->r0, 0);
> -        dc->r0_set = true;
> -    }
> -    return dc->r0;
> +    return tcg_constant_i32(0);
>  }
>  
>  static TCGv_i32 reg_for_write(DisasContext *dc, int reg)
> @@ -194,10 +184,7 @@ static TCGv_i32 reg_for_write(DisasContext *dc, int reg)
>      if (likely(reg != 0)) {
>          return cpu_R[reg];
>      }
> -    if (dc->r0 == NULL) {
> -        dc->r0 = tcg_temp_new_i32();
> -    }
> -    return dc->r0;
> +    return tcg_temp_new_i32();
>  }
>  
>  static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects,
> @@ -1635,8 +1622,6 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
>      dc->cfg = &cpu->cfg;
>      dc->tb_flags = dc->base.tb->flags;
>      dc->ext_imm = dc->base.tb->cs_base;
> -    dc->r0 = NULL;
> -    dc->r0_set = false;
>      dc->mem_index = cpu_mmu_index(cs, false);
>      dc->jmp_cond = dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NEVER;
>      dc->jmp_dest = -1;
> @@ -1675,11 +1660,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
>          trap_illegal(dc, true);
>      }
>  
> -    if (dc->r0) {
> -        dc->r0 = NULL;
> -        dc->r0_set = false;
> -    }
> -
>      /* Discard the imm global when its contents cannot be used. */
>      if ((dc->tb_flags & ~dc->tb_flags_to_set) & IMM_FLAG) {
>          tcg_gen_discard_i32(cpu_imm);
> -- 
> 2.43.0
> 

[PATCH v2 10/10] target/microblaze: Simplify compute_ldst_addr_type{a, b}

[Richard Henderson]

Require TCGv_i32 and TCGv be identical, so drop
the extensions.  Return constants when possible
instead of a mov into a temporary.  Return register
inputs unchanged when possible.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/translate.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 047d97e2c5..5098a1db4d 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -606,19 +606,18 @@ DO_TYPEBI(xori, false, tcg_gen_xori_i32)
 
 static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
 {
-    TCGv ret = tcg_temp_new();
+    TCGv ret;
 
     /* If any of the regs is r0, set t to the value of the other reg.  */
     if (ra && rb) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]);
-        tcg_gen_extu_i32_tl(ret, tmp);
+        ret = tcg_temp_new_i32();
+        tcg_gen_add_i32(ret, cpu_R[ra], cpu_R[rb]);
     } else if (ra) {
-        tcg_gen_extu_i32_tl(ret, cpu_R[ra]);
+        ret = cpu_R[ra];
     } else if (rb) {
-        tcg_gen_extu_i32_tl(ret, cpu_R[rb]);
+        ret = cpu_R[rb];
     } else {
-        tcg_gen_movi_tl(ret, 0);
+        ret = tcg_constant_i32(0);
     }
 
     if ((ra == 1 || rb == 1) && dc->cfg->stackprot) {
@@ -629,15 +628,16 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
 
 static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm)
 {
-    TCGv ret = tcg_temp_new();
+    TCGv ret;
 
     /* If any of the regs is r0, set t to the value of the other reg.  */
-    if (ra) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_addi_i32(tmp, cpu_R[ra], imm);
-        tcg_gen_extu_i32_tl(ret, tmp);
+    if (ra && imm) {
+        ret = tcg_temp_new_i32();
+        tcg_gen_addi_i32(ret, cpu_R[ra], imm);
+    } else if (ra) {
+        ret = cpu_R[ra];
     } else {
-        tcg_gen_movi_tl(ret, (uint32_t)imm);
+        ret = tcg_constant_i32(imm);
     }
 
     if (ra == 1 && dc->cfg->stackprot) {
-- 
2.43.0

Re: [PATCH v2 10/10] target/microblaze: Simplify compute_ldst_addr_type{a,b}

[Edgar E. Iglesias]

On Sun, May 25, 2025 at 05:02:20PM +0100, Richard Henderson wrote:
> Require TCGv_i32 and TCGv be identical, so drop
> the extensions.  Return constants when possible
> instead of a mov into a temporary.  Return register
> inputs unchanged when possible.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>



> ---
>  target/microblaze/translate.c | 26 +++++++++++++-------------
>  1 file changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 047d97e2c5..5098a1db4d 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -606,19 +606,18 @@ DO_TYPEBI(xori, false, tcg_gen_xori_i32)
>  
>  static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
>  {
> -    TCGv ret = tcg_temp_new();
> +    TCGv ret;
>  
>      /* If any of the regs is r0, set t to the value of the other reg.  */
>      if (ra && rb) {
> -        TCGv_i32 tmp = tcg_temp_new_i32();
> -        tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]);
> -        tcg_gen_extu_i32_tl(ret, tmp);
> +        ret = tcg_temp_new_i32();
> +        tcg_gen_add_i32(ret, cpu_R[ra], cpu_R[rb]);
>      } else if (ra) {
> -        tcg_gen_extu_i32_tl(ret, cpu_R[ra]);
> +        ret = cpu_R[ra];
>      } else if (rb) {
> -        tcg_gen_extu_i32_tl(ret, cpu_R[rb]);
> +        ret = cpu_R[rb];
>      } else {
> -        tcg_gen_movi_tl(ret, 0);
> +        ret = tcg_constant_i32(0);
>      }
>  
>      if ((ra == 1 || rb == 1) && dc->cfg->stackprot) {
> @@ -629,15 +628,16 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
>  
>  static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm)
>  {
> -    TCGv ret = tcg_temp_new();
> +    TCGv ret;
>  
>      /* If any of the regs is r0, set t to the value of the other reg.  */
> -    if (ra) {
> -        TCGv_i32 tmp = tcg_temp_new_i32();
> -        tcg_gen_addi_i32(tmp, cpu_R[ra], imm);
> -        tcg_gen_extu_i32_tl(ret, tmp);
> +    if (ra && imm) {
> +        ret = tcg_temp_new_i32();
> +        tcg_gen_addi_i32(ret, cpu_R[ra], imm);
> +    } else if (ra) {
> +        ret = cpu_R[ra];
>      } else {
> -        tcg_gen_movi_tl(ret, (uint32_t)imm);
> +        ret = tcg_constant_i32(imm);
>      }
>  
>      if (ra == 1 && dc->cfg->stackprot) {
> -- 
> 2.43.0
>