From: Wei Liu <wei.liu@kernel.org>
To: Magnus Kulke <magnuskulke@linux.microsoft.com>
Cc: "Wei Liu" <wei.liu@kernel.org>,
magnuskulke@microsoft.com, qemu-devel@nongnu.org,
liuwe@microsoft.com, "Paolo Bonzini" <pbonzini@redhat.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Phil Dennis-Jordan" <phil@philjordan.eu>,
"Roman Bolshakov" <rbolshakov@ddn.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Zhao Liu" <zhao1.liu@intel.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Cameron Esfahani" <dirty@apple.com>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Daniel P. Berrangé" <berrange@redhat.com>,
jinankjain@microsoft.com, muislam@microsoft.com
Subject: Re: [RFC PATCH 18/25] target/i386/mshv: Implement mshv_arch_put_registers()
Date: Fri, 6 Jun 2025 19:16:10 +0000 [thread overview]
Message-ID: <aEM-epmqAv3kiwjX@liuwe-devbox-ubuntu-v2.tail21d00.ts.net> (raw)
In-Reply-To: <aDceHy3zjGgwBFNm@example.com>
On Wed, May 28, 2025 at 04:30:55PM +0200, Magnus Kulke wrote:
> On Tue, May 20, 2025 at 10:22:27PM +0000, Wei Liu wrote:
> > On Tue, May 20, 2025 at 01:30:11PM +0200, Magnus Kulke wrote:
> > > + /*
> > > + * TODO: support asserting an interrupt using interrup_bitmap
> > > + * it should be possible if we use the vm_fd
> > > + */
> > > +
> >
> > Why is there a need to assert an interrupt here?
> >
>
> The comment has been carried over from the mshv-ioctl crate:
>
> https://github.com/rust-vmm/mshv/blob/main/mshv-ioctls/src/ioctls/vcpu.rs#L778
>
> I was wondering whether we can/want to set the bitmap here, since we do
> have access to the vm_fd, but I didn't follow up on that yet.
In the code snippet you quoted, an error is returned if the bitmap is
not empty.
Please at least print a warning if the bitmap is not empty to catch any
issues. Debugging lost interrupts is hard enough as it is.
CC the Rust-VMM code co-owners for awareness.
Thanks,
Wei.
next prev parent reply other threads:[~2025-06-06 19:17 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-20 11:29 [RFC PATCH 00/25] Implementing a MSHV (Microsoft Hypervisor) accelerator Magnus Kulke
2025-05-20 11:29 ` [RFC PATCH 01/25] accel: Add Meson and config support for MSHV accelerator Magnus Kulke
2025-05-20 11:50 ` Daniel P. Berrangé
2025-05-20 14:16 ` Paolo Bonzini
2025-05-20 11:29 ` [RFC PATCH 02/25] target/i386/emulate: allow instruction decoding from stream Magnus Kulke
2025-05-20 12:42 ` Paolo Bonzini
2025-05-20 17:29 ` Wei Liu
2025-05-20 11:29 ` [RFC PATCH 03/25] target/i386/mshv: Add x86 decoder/emu implementation Magnus Kulke
2025-05-20 11:54 ` Daniel P. Berrangé
2025-05-20 13:17 ` Paolo Bonzini
2025-05-20 17:36 ` Wei Liu
2025-05-20 11:29 ` [RFC PATCH 04/25] hw/intc: Generalize APIC helper names from kvm_* to accel_* Magnus Kulke
2025-05-20 11:29 ` [RFC PATCH 05/25] include/hw/hyperv: Add MSHV ABI header definitions Magnus Kulke
2025-05-20 14:24 ` Paolo Bonzini
2025-05-20 11:29 ` [RFC PATCH 06/25] accel/mshv: Add accelerator skeleton Magnus Kulke
2025-05-20 12:02 ` Daniel P. Berrangé
2025-05-20 12:38 ` Paolo Bonzini
2025-05-20 11:30 ` [RFC PATCH 07/25] accel/mshv: Register memory region listeners Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 08/25] accel/mshv: Initialize VM partition Magnus Kulke
2025-05-20 19:07 ` Wei Liu
2025-05-22 15:42 ` Magnus Kulke
2025-05-22 17:46 ` Wei Liu
2025-05-23 8:23 ` Magnus Kulke
2025-05-23 15:37 ` Wei Liu
2025-05-23 16:13 ` Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 09/25] accel/mshv: Register guest memory regions with hypervisor Magnus Kulke
2025-05-20 20:07 ` Wei Liu
2025-05-23 14:17 ` Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 10/25] accel/mshv: Add ioeventfd support Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 11/25] accel/mshv: Add basic interrupt injection support Magnus Kulke
2025-05-20 14:18 ` Paolo Bonzini
2025-05-20 20:15 ` Wei Liu
2025-05-27 16:27 ` Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 12/25] accel/mshv: Add vCPU creation and execution loop Magnus Kulke
2025-05-20 13:50 ` Paolo Bonzini
2025-05-20 13:54 ` Paolo Bonzini
2025-05-23 17:05 ` Wei Liu
2025-06-06 23:06 ` Nuno Das Neves
2025-05-20 11:30 ` [RFC PATCH 13/25] accel/mshv: Add vCPU signal handling Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 14/25] target/i386/mshv: Add CPU create and remove logic Magnus Kulke
2025-05-20 21:50 ` Wei Liu
2025-05-20 11:30 ` [RFC PATCH 15/25] target/i386/mshv: Implement mshv_store_regs() Magnus Kulke
2025-05-20 22:07 ` Wei Liu
2025-05-20 11:30 ` [RFC PATCH 16/25] target/i386/mshv: Implement mshv_get_standard_regs() Magnus Kulke
2025-05-20 22:09 ` Wei Liu
2025-05-20 11:30 ` [RFC PATCH 17/25] target/i386/mshv: Implement mshv_get_special_regs() Magnus Kulke
2025-05-20 14:05 ` Paolo Bonzini
2025-05-20 22:15 ` Wei Liu
2025-05-28 13:55 ` Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 18/25] target/i386/mshv: Implement mshv_arch_put_registers() Magnus Kulke
2025-05-20 14:33 ` Paolo Bonzini
2025-05-20 22:22 ` Wei Liu
2025-05-28 14:30 ` Magnus Kulke
2025-06-06 19:16 ` Wei Liu [this message]
2025-06-06 19:11 ` Wei Liu
2025-05-20 11:30 ` [RFC PATCH 19/25] target/i386/mshv: Set local interrupt controller state Magnus Kulke
2025-05-20 14:03 ` Paolo Bonzini
2025-05-20 11:30 ` [RFC PATCH 20/25] target/i386/mshv: Register CPUID entries with MSHV Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 21/25] target/i386/mshv: Register MSRs " Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 22/25] target/i386/mshv: Integrate x86 instruction decoder/emulator Magnus Kulke
2025-05-20 22:38 ` Wei Liu
2025-05-28 15:10 ` Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 23/25] target/i386/mshv: Write MSRs to the hypervisor Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 24/25] target/i386/mshv: Implement mshv_vcpu_run() Magnus Kulke
2025-05-20 13:21 ` Paolo Bonzini
2025-05-20 22:52 ` Wei Liu
2025-06-03 15:40 ` Magnus Kulke
2025-07-01 8:35 ` Magnus Kulke
2025-07-01 15:11 ` Wei Liu
2025-07-01 15:45 ` Magnus Kulke
2025-07-01 15:47 ` Wei Liu
2025-07-01 15:51 ` Magnus Kulke
2025-05-20 11:30 ` [RFC PATCH 25/25] accel/mshv: Add memory remapping workaround Magnus Kulke
2025-05-20 13:53 ` Paolo Bonzini
2025-05-22 12:51 ` Magnus Kulke
2025-05-20 14:25 ` [RFC PATCH 00/25] Implementing a MSHV (Microsoft Hypervisor) accelerator Paolo Bonzini
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