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Mon, 23 Jun 2025 06:15:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFcQJgXCC48/xNSgvpGU4DGTnrnL032LX1AxGSFFBI42enGRCY/wS1JQbfbAVvTPZNl5zv+EA== X-Received: by 2002:a05:6214:5081:b0:6fa:fe02:81ff with SMTP id 6a1803df08f44-6fd0a43b6a8mr191051006d6.3.1750684546940; Mon, 23 Jun 2025 06:15:46 -0700 (PDT) Received: from x1.local ([85.131.185.92]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6fd09456a98sm44490936d6.49.2025.06.23.06.15.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jun 2025 06:15:46 -0700 (PDT) Date: Mon, 23 Jun 2025 09:15:43 -0400 From: Peter Xu To: CLEMENT MATHIEU--DRIF Cc: "qemu-devel@nongnu.org" , "pbonzini@redhat.com" , "david@redhat.com" , "philmd@linaro.org" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , Ethan MILON Subject: Re: [PATCH 0/2] Memory and PCI definitions for emulated ATS Message-ID: References: <20250620055620.133027-1-clement.mathieu--drif@eviden.com> <7ba298b6-13d3-44b4-bc67-5516893a6cb4@eviden.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <7ba298b6-13d3-44b4-bc67-5516893a6cb4@eviden.com> Received-SPF: pass client-ip=170.10.133.124; envelope-from=peterx@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Jun 23, 2025 at 05:43:06AM +0000, CLEMENT MATHIEU--DRIF wrote: > Hi Peter > > On 20/06/2025 4:35 pm, Peter Xu wrote: > > Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. > > > > > > On Fri, Jun 20, 2025 at 05:56:49AM +0000, CLEMENT MATHIEU--DRIF wrote: > >> This short series adds the 'address type' bit (concept from PCIe) to the > >> memory attributes and extends the IOMMUAccessFlags enum. This > >> will be required to implement ATS support for the virtual IOMMUs. > >> > >> Address type: Field present in the PCIe R/W requests, it allows devices to > >> tell the IOMMU if the address provided in the request is physical or not. > >> In other words, it allows the devices to use a physical address obtained > >> via ATS and to prevent the IOMMU from trying to remap it on the fly. > > > > Two pure questions on the flags, could be relevant to spec: > > > >> > >> Additional IOMMU access flags: > >> - Execute Requested > > > > Does this mean that we can start to put code into DMA regions so that > > device can run some day (even if the device may have a core that is totally > > different arch v.s. the host's > AFAIU, the spec is so nonrestrictive about this flag that heterogeneous > arch should not be an issue. > > "The definition of what it means for a Function to execute code is > outside the scope of this specification" > > > > >> - Privileged Mode Requested > >> - Global > >> - Untranslated Only (cannot be used with 'Address type = translated') > > > > I can understand this with patch 1, but not yet with patch 2. > > > > Patch 1 makes sense to me, IIUC it means the addresses to be used in a pcie > > request will be translated addresses which should bypass IOMMU DMAR. > > > > OTOH, patch 2 added it into iotlb access permissions, which I'm not sure > > what does it mean. Perhaps those addresses can only be translated by ATS > > pre-translation requests, so that DMA on top of them (in IOVA address > > space) will directly fail? > > I put this here because the ATS API returns IOMMUTLBEntry structures, > which contain these flags. > > The untranslated-only bit is set in ATS responses to inform the device > that the requested address cannot be pre-translated and should be > translated on the fly by the DMA remapping engine. The interrupt range > commonly falls into this category. Ah I see. Yes this makes sense. > > > > > Side note, it might still be more reasonable to put these changes into the > > ATS series as the first user of flags. > > Yes, I can do that. > However, the ATS series will contain ~10/~12 patches, is it a concern? Considering the size of this series, IMHO it should be better to stick with when they're uesd. Thanks, -- Peter Xu