[PATCH 0/4] Add support for gb200-bmc machine

[PATCH 0/4] Add support for gb200-bmc machine

[Ed Tanous]

This patch series adds support for gb200-bmc, a baseboard management controller
module based on an Aspeed 2600 SOC.

Ed Tanous (4):
  hw/arm: Add PCA9554 to ARM target
  hw/arm/aspeed: Add second SPI chip to Aspeed model
  docs: add support for gb200-bmc
  hw/arm/aspeed: Add GB200 BMC target

 docs/system/arm/aspeed.rst |  4 +-
 hw/arm/Kconfig             |  1 +
 hw/arm/aspeed.c            | 81 ++++++++++++++++++++++++++++++++++++++
 hw/arm/aspeed_eeprom.c     | 21 ++++++++++
 hw/arm/aspeed_eeprom.h     |  3 ++
 include/hw/arm/aspeed.h    |  2 +
 6 files changed, 110 insertions(+), 2 deletions(-)

-- 
2.43.0

[PATCH 1/4] hw/arm: Add PCA9554 to ARM target

[Ed Tanous]

From: Ed Tanous <ed@tanous.net>

There are arm targets that are connected to this io expander,
specifically some varieties of Aspeed 2600 BMCs.  Add it to Kconfig to
allow use.

Signed-off-by: Ed Tanous <etanous@nvidia.com>
---
 hw/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index f543d944c3..6ea86534d5 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -532,6 +532,7 @@ config ASPEED_SOC
     select I2C
     select DPS310
     select PCA9552
+    select PCA9554
     select SERIAL_MM
     select SMBUS_EEPROM
     select PCA954X
-- 
2.43.0

Re: [PATCH 1/4] hw/arm: Add PCA9554 to ARM target

[Cédric Le Goater]

Hello Ed,

On 7/1/25 22:33, Ed Tanous wrote:
> From: Ed Tanous <ed@tanous.net>
> 
> There are arm targets that are connected to this io expander,
> specifically some varieties of Aspeed 2600 BMCs.  Add it to Kconfig to
> allow use.
> 
> Signed-off-by: Ed Tanous <etanous@nvidia.com>
> ---
>   hw/arm/Kconfig | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index f543d944c3..6ea86534d5 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -532,6 +532,7 @@ config ASPEED_SOC
>       select I2C
>       select DPS310
>       select PCA9552
> +    select PCA9554
>       select SERIAL_MM
>       select SMBUS_EEPROM
>       select PCA954X


This was already added by Patrick in patch :

   https://lore.kernel.org/qemu-devel/20250619151458.2831859-1-patrick@stwcx.xyz/

which should be pushed by the end the week.

Thanks,

C.

Re: [PATCH 1/4] hw/arm: Add PCA9554 to ARM target

[Philippe Mathieu-Daudé]

Hi,

On 2/7/25 08:47, Cédric Le Goater wrote:
> Hello Ed,
> 
> On 7/1/25 22:33, Ed Tanous wrote:
>> From: Ed Tanous <ed@tanous.net>
>>
>> There are arm targets that are connected to this io expander,
>> specifically some varieties of Aspeed 2600 BMCs.  Add it to Kconfig to
>> allow use.
>>
>> Signed-off-by: Ed Tanous <etanous@nvidia.com>
>> ---
>>   hw/arm/Kconfig | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
>> index f543d944c3..6ea86534d5 100644
>> --- a/hw/arm/Kconfig
>> +++ b/hw/arm/Kconfig
>> @@ -532,6 +532,7 @@ config ASPEED_SOC
>>       select I2C
>>       select DPS310
>>       select PCA9552
>> +    select PCA9554

Note, these i2c devices 1/ aren't part of the SoC, but boards/machines,
2/ nor are they required to have a functional machine (i.e. a i2c link
could get cut or an i2c device ending dead).

I'd prefer 1/ add a ASPEED_MACHINE layer selecting ASPEED_SOC and the
external devices, and 2/ use "imply" statement instead of "select" for
devices, as per docs/devel/kconfig.rst:

   Boards specify their constituent devices using ``imply`` and
   ``select`` directives.  A device should be listed under ``select``
   if the board cannot be started at all without it.  It should be
   listed under ``imply`` if (depending on the QEMU command line)
   the board may or may not be started without it.  Boards default to
   true, but also have a ``depends on`` clause to limit them to the
   appropriate targets.
   For some targets, not all boards may be supported by hardware
   virtualization, in which case they also depend on the ``TCG``
   symbol, other symbols that are commonly used as dependencies for
   boards include libraries (such as ``FDT``) or ``TARGET_BIG_ENDIAN``
   (possibly negated).

My 2 cents.

Regards,

Phil.

Re: [PATCH 1/4] hw/arm: Add PCA9554 to ARM target

[etanous via]

On Wed, Jul 02, 2025 at 09:04:25AM +0200, Philippe Mathieu-Daudé wrote:
> 
> Hi,
> 
> On 2/7/25 08:47, Cédric Le Goater wrote:
> > Hello Ed,
> > 
> > On 7/1/25 22:33, Ed Tanous wrote:
> > > From: Ed Tanous <ed@tanous.net>
> > > 
> > > There are arm targets that are connected to this io expander,
> > > specifically some varieties of Aspeed 2600 BMCs.  Add it to Kconfig to
> > > allow use.
> > > 
> > > Signed-off-by: Ed Tanous <etanous@nvidia.com>
> > > ---
> > >   hw/arm/Kconfig | 1 +
> > >   1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> > > index f543d944c3..6ea86534d5 100644
> > > --- a/hw/arm/Kconfig
> > > +++ b/hw/arm/Kconfig
> > > @@ -532,6 +532,7 @@ config ASPEED_SOC
> > >       select I2C
> > >       select DPS310
> > >       select PCA9552
> > > +    select PCA9554
> 
> Note, these i2c devices 1/ aren't part of the SoC, but boards/machines,
> 2/ nor are they required to have a functional machine (i.e. a i2c link
> could get cut or an i2c device ending dead).
> 
> I'd prefer 1/ add a ASPEED_MACHINE layer selecting ASPEED_SOC and the
> external devices, and 2/ use "imply" statement instead of "select" for
> devices, as per docs/devel/kconfig.rst:
> 
>   Boards specify their constituent devices using ``imply`` and
>   ``select`` directives.  A device should be listed under ``select``
>   if the board cannot be started at all without it.  It should be
>   listed under ``imply`` if (depending on the QEMU command line)
>   the board may or may not be started without it.  Boards default to
>   true, but also have a ``depends on`` clause to limit them to the
>   appropriate targets.
>   For some targets, not all boards may be supported by hardware
>   virtualization, in which case they also depend on the ``TCG``
>   symbol, other symbols that are commonly used as dependencies for
>   boards include libraries (such as ``FDT``) or ``TARGET_BIG_ENDIAN``
>   (possibly negated).
> 

ACK, seems reasonable.  I tried to follow the pattern that was there,
but agreed, it was odd that "board" level things were added at the ARM
layer.

> My 2 cents.
> 
> Regards,
> 
> Phil.

Re: [PATCH 1/4] hw/arm: Add PCA9554 to ARM target

[Cédric Le Goater]

On 7/2/25 21:20, etanous wrote:
> On Wed, Jul 02, 2025 at 09:04:25AM +0200, Philippe Mathieu-Daudé wrote:
>>
>> Hi,
>>
>> On 2/7/25 08:47, Cédric Le Goater wrote:
>>> Hello Ed,
>>>
>>> On 7/1/25 22:33, Ed Tanous wrote:
>>>> From: Ed Tanous <ed@tanous.net>
>>>>
>>>> There are arm targets that are connected to this io expander,
>>>> specifically some varieties of Aspeed 2600 BMCs.  Add it to Kconfig to
>>>> allow use.
>>>>
>>>> Signed-off-by: Ed Tanous <etanous@nvidia.com>
>>>> ---
>>>>    hw/arm/Kconfig | 1 +
>>>>    1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
>>>> index f543d944c3..6ea86534d5 100644
>>>> --- a/hw/arm/Kconfig
>>>> +++ b/hw/arm/Kconfig
>>>> @@ -532,6 +532,7 @@ config ASPEED_SOC
>>>>        select I2C
>>>>        select DPS310
>>>>        select PCA9552
>>>> +    select PCA9554
>>
>> Note, these i2c devices 1/ aren't part of the SoC, but boards/machines,
>> 2/ nor are they required to have a functional machine (i.e. a i2c link
>> could get cut or an i2c device ending dead).
>>
>> I'd prefer 1/ add a ASPEED_MACHINE layer selecting ASPEED_SOC and the
>> external devices, and 2/ use "imply" statement instead of "select" for
>> devices, as per docs/devel/kconfig.rst:
>>
>>    Boards specify their constituent devices using ``imply`` and
>>    ``select`` directives.  A device should be listed under ``select``
>>    if the board cannot be started at all without it.  It should be
>>    listed under ``imply`` if (depending on the QEMU command line)
>>    the board may or may not be started without it.  Boards default to
>>    true, but also have a ``depends on`` clause to limit them to the
>>    appropriate targets.
>>    For some targets, not all boards may be supported by hardware
>>    virtualization, in which case they also depend on the ``TCG``
>>    symbol, other symbols that are commonly used as dependencies for
>>    boards include libraries (such as ``FDT``) or ``TARGET_BIG_ENDIAN``
>>    (possibly negated).
>>
> 
> ACK, seems reasonable.  I tried to follow the pattern that was there,
> but agreed, it was odd that "board" level things were added at the ARM
> layer.
ASPEED_SOC has been there since the beginning; when the timer
model was first introduced. Kconfig was introduced, then meson.
We simply kept using it.

ASPEED_MACHINE would be nice. We would still have to "select"
all I2C devices because the devices are always created at init
time even with -nodefaults. These device are soldered on the
board and it doesn't make sense to make them optional. IIRC,
we have flexibility to choose the SPI flash devices though,
this is because real systems have sockets to replace them.

Anyhow, if you want to tackle this, you are welcome.

Thanks,

C.

Re: [PATCH 1/4] hw/arm: Add PCA9554 to ARM target

[etanous via]

On Wed, Jul 02, 2025 at 08:47:48AM +0200, Cédric Le Goater wrote:
> 
> 
> 
> 
> This was already added by Patrick in patch :
>

ACK.  Will remove this patch in next series.

[PATCH 2/4] hw/arm/aspeed: Add second SPI chip to Aspeed model

[Ed Tanous]

Aspeed2600 has two spi lanes;  Add a new struct that can mount the
second SPI.

Signed-off-by: Ed Tanous <etanous@nvidia.com>
---
 hw/arm/aspeed.c         | 2 ++
 include/hw/arm/aspeed.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index d0b333646e..3ef7f6c5b2 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -465,6 +465,8 @@ static void aspeed_machine_init(MachineState *machine)
         aspeed_board_init_flashes(&bmc->soc->spi[0],
                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
                               1, amc->num_cs);
+        aspeed_board_init_flashes(&bmc->soc->spi[1],
+                                  amc->spi2_model, 1, amc->num_cs2);
     }
 
     if (machine->kernel_filename && sc->num_cpus > 1) {
diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
index 973277bea6..6c36455656 100644
--- a/include/hw/arm/aspeed.h
+++ b/include/hw/arm/aspeed.h
@@ -35,7 +35,9 @@ struct AspeedMachineClass {
     uint32_t hw_strap2;
     const char *fmc_model;
     const char *spi_model;
+    const char *spi2_model;
     uint32_t num_cs;
+    uint32_t num_cs2;
     uint32_t macs_mask;
     void (*i2c_init)(AspeedMachineState *bmc);
     uint32_t uart_default;
-- 
2.43.0

Re: [PATCH 2/4] hw/arm/aspeed: Add second SPI chip to Aspeed model

[Cédric Le Goater]

On 7/1/25 22:33, Ed Tanous wrote:
> Aspeed2600 has two spi lanes;  Add a new struct that can mount the
> second SPI.
> 
> Signed-off-by: Ed Tanous <etanous@nvidia.com>
> ---
>   hw/arm/aspeed.c         | 2 ++
>   include/hw/arm/aspeed.h | 2 ++
>   2 files changed, 4 insertions(+)
> 
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index d0b333646e..3ef7f6c5b2 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -465,6 +465,8 @@ static void aspeed_machine_init(MachineState *machine)
>           aspeed_board_init_flashes(&bmc->soc->spi[0],
>                                 bmc->spi_model ? bmc->spi_model : amc->spi_model,
>                                 1, amc->num_cs);
> +        aspeed_board_init_flashes(&bmc->soc->spi[1],
> +                                  amc->spi2_model, 1, amc->num_cs2);
>       }
>   
>       if (machine->kernel_filename && sc->num_cpus > 1) {
> diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
> index 973277bea6..6c36455656 100644
> --- a/include/hw/arm/aspeed.h
> +++ b/include/hw/arm/aspeed.h
> @@ -35,7 +35,9 @@ struct AspeedMachineClass {
>       uint32_t hw_strap2;
>       const char *fmc_model;
>       const char *spi_model;
> +    const char *spi2_model;
>       uint32_t num_cs;
> +    uint32_t num_cs2;
>       uint32_t macs_mask;
>       void (*i2c_init)(AspeedMachineState *bmc);
>       uint32_t uart_default;

Another way specifying backends for all SPI devices is to use -blockdev :

   $ qemu-system-arm -M ast2600-evb \
       -blockdev node-name=fmc0,driver=file,filename=/path/to/fmc0.img \
       -device mx66u51235f,bus=ssi.0,cs=0x0,drive=fmc0 \
       -blockdev node-name=fmc1,driver=file,filename=/path/to/fmc1.img \
       -device mx66u51235f,bus=ssi.0,cs=0x1,drive=fmc1 \
       -blockdev node-name=spi1,driver=file,filename=/path/to/spi1.img \
       -device mx66u51235f,cs=0x0,bus=ssi.1,drive=spi1 \
       -nographic -nodefaults

See https://www.qemu.org/docs/master/system/arm/aspeed.html.

Have you tried it ?


Thanks,

C.

Re: [PATCH 2/4] hw/arm/aspeed: Add second SPI chip to Aspeed model

[etanous via]

On Wed, Jul 02, 2025 at 09:00:20AM +0200, Cédric Le Goater wrote:
> External email: Use caution opening links or attachments
> 
> 
> On 7/1/25 22:33, Ed Tanous wrote:
> > Aspeed2600 has two spi lanes;  Add a new struct that can mount the
> > second SPI.
> > 
> > Signed-off-by: Ed Tanous <etanous@nvidia.com>
> > ---
> >   hw/arm/aspeed.c         | 2 ++
> >   include/hw/arm/aspeed.h | 2 ++
> >   2 files changed, 4 insertions(+)
> > 
> > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> > index d0b333646e..3ef7f6c5b2 100644
> > --- a/hw/arm/aspeed.c
> > +++ b/hw/arm/aspeed.c
> > @@ -465,6 +465,8 @@ static void aspeed_machine_init(MachineState *machine)
> >           aspeed_board_init_flashes(&bmc->soc->spi[0],
> >                                 bmc->spi_model ? bmc->spi_model : amc->spi_model,
> >                                 1, amc->num_cs);
> > +        aspeed_board_init_flashes(&bmc->soc->spi[1],
> > +                                  amc->spi2_model, 1, amc->num_cs2);
> >       }
> > 
> >       if (machine->kernel_filename && sc->num_cpus > 1) {
> > diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
> > index 973277bea6..6c36455656 100644
> > --- a/include/hw/arm/aspeed.h
> > +++ b/include/hw/arm/aspeed.h
> > @@ -35,7 +35,9 @@ struct AspeedMachineClass {
> >       uint32_t hw_strap2;
> >       const char *fmc_model;
> >       const char *spi_model;
> > +    const char *spi2_model;
> >       uint32_t num_cs;
> > +    uint32_t num_cs2;
> >       uint32_t macs_mask;
> >       void (*i2c_init)(AspeedMachineState *bmc);
> >       uint32_t uart_default;
> 
> Another way specifying backends for all SPI devices is to use -blockdev :
> 
>   $ qemu-system-arm -M ast2600-evb \
>       -blockdev node-name=fmc0,driver=file,filename=/path/to/fmc0.img \
>       -device mx66u51235f,bus=ssi.0,cs=0x0,drive=fmc0 \
>       -blockdev node-name=fmc1,driver=file,filename=/path/to/fmc1.img \
>       -device mx66u51235f,bus=ssi.0,cs=0x1,drive=fmc1 \
>       -blockdev node-name=spi1,driver=file,filename=/path/to/spi1.img \
>       -device mx66u51235f,cs=0x0,bus=ssi.1,drive=spi1 \
>       -nographic -nodefaults
> 

I had attempted that at one point.  The second SPI flash is expected to
be empty on first boot, so building up an empty file with dd seemed like
a waste, and pushed more details on the user calling the machine to
know the machine configuration.  FWIW, yoctos 'runqemu' helper script is
also very useful, but getting it to spit out non-standard args and files
isn't the easiest.  If what's in this patch is ok, I'd like to stick
with it.  If not, I can dig deeper into trying to do this on command
line.

> See <LINK SCRUBBED>
> 
> Have you tried it ?
> 
> 
> Thanks,
> 
> C.
> 
> 

Re: [PATCH 2/4] hw/arm/aspeed: Add second SPI chip to Aspeed model

[Cédric Le Goater]

On 7/2/25 21:27, etanous wrote:
> On Wed, Jul 02, 2025 at 09:00:20AM +0200, Cédric Le Goater wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> On 7/1/25 22:33, Ed Tanous wrote:
>>> Aspeed2600 has two spi lanes;  Add a new struct that can mount the
>>> second SPI.
>>>
>>> Signed-off-by: Ed Tanous <etanous@nvidia.com>
>>> ---
>>>    hw/arm/aspeed.c         | 2 ++
>>>    include/hw/arm/aspeed.h | 2 ++
>>>    2 files changed, 4 insertions(+)
>>>
>>> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
>>> index d0b333646e..3ef7f6c5b2 100644
>>> --- a/hw/arm/aspeed.c
>>> +++ b/hw/arm/aspeed.c
>>> @@ -465,6 +465,8 @@ static void aspeed_machine_init(MachineState *machine)
>>>            aspeed_board_init_flashes(&bmc->soc->spi[0],
>>>                                  bmc->spi_model ? bmc->spi_model : amc->spi_model,
>>>                                  1, amc->num_cs);
>>> +        aspeed_board_init_flashes(&bmc->soc->spi[1],
>>> +                                  amc->spi2_model, 1, amc->num_cs2);
>>>        }
>>>
>>>        if (machine->kernel_filename && sc->num_cpus > 1) {
>>> diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
>>> index 973277bea6..6c36455656 100644
>>> --- a/include/hw/arm/aspeed.h
>>> +++ b/include/hw/arm/aspeed.h
>>> @@ -35,7 +35,9 @@ struct AspeedMachineClass {
>>>        uint32_t hw_strap2;
>>>        const char *fmc_model;
>>>        const char *spi_model;
>>> +    const char *spi2_model;
>>>        uint32_t num_cs;
>>> +    uint32_t num_cs2;
>>>        uint32_t macs_mask;
>>>        void (*i2c_init)(AspeedMachineState *bmc);
>>>        uint32_t uart_default;
>>
>> Another way specifying backends for all SPI devices is to use -blockdev :
>>
>>    $ qemu-system-arm -M ast2600-evb \
>>        -blockdev node-name=fmc0,driver=file,filename=/path/to/fmc0.img \
>>        -device mx66u51235f,bus=ssi.0,cs=0x0,drive=fmc0 \
>>        -blockdev node-name=fmc1,driver=file,filename=/path/to/fmc1.img \
>>        -device mx66u51235f,bus=ssi.0,cs=0x1,drive=fmc1 \
>>        -blockdev node-name=spi1,driver=file,filename=/path/to/spi1.img \
>>        -device mx66u51235f,cs=0x0,bus=ssi.1,drive=spi1 \
>>        -nographic -nodefaults
>>
> 
> I had attempted that at one point.  The second SPI flash is expected to
> be empty on first boot, so building up an empty file with dd seemed like
> a waste, and pushed more details on the user calling the machine to
> know the machine configuration.  FWIW, yoctos 'runqemu' helper script is
> also very useful, but getting it to spit out non-standard args and files
> isn't the easiest.  If what's in this patch is ok, I'd like to stick
> with it.  If not, I can dig deeper into trying to do this on command
> line.

It's fine. we will merge it. I am trying to promote the -blockdev interface
to get rid of -drive but this seems to be wishful thinking.


Thanks,

C.

Re: [PATCH 2/4] hw/arm/aspeed: Add second SPI chip to Aspeed model

[Cédric Le Goater]

On 7/1/25 22:33, Ed Tanous wrote:
> Aspeed2600 has two spi lanes;  Add a new struct that can mount the
> second SPI.
> 
> Signed-off-by: Ed Tanous <etanous@nvidia.com>
> ---
>   hw/arm/aspeed.c         | 2 ++
>   include/hw/arm/aspeed.h | 2 ++
>   2 files changed, 4 insertions(+)
> 
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index d0b333646e..3ef7f6c5b2 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -465,6 +465,8 @@ static void aspeed_machine_init(MachineState *machine)
>           aspeed_board_init_flashes(&bmc->soc->spi[0],
>                                 bmc->spi_model ? bmc->spi_model : amc->spi_model,
>                                 1, amc->num_cs);
> +        aspeed_board_init_flashes(&bmc->soc->spi[1],
> +                                  amc->spi2_model, 1, amc->num_cs2);
>       }
>   
>       if (machine->kernel_filename && sc->num_cpus > 1) {
> diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
> index 973277bea6..6c36455656 100644
> --- a/include/hw/arm/aspeed.h
> +++ b/include/hw/arm/aspeed.h
> @@ -35,7 +35,9 @@ struct AspeedMachineClass {
>       uint32_t hw_strap2;
>       const char *fmc_model;
>       const char *spi_model;
> +    const char *spi2_model;
>       uint32_t num_cs;
> +    uint32_t num_cs2;
>       uint32_t macs_mask;
>       void (*i2c_init)(AspeedMachineState *bmc);
>       uint32_t uart_default;


Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.

[PATCH 3/4] docs: add support for gb200-bmc

[Ed Tanous]

This patch updates the docs for support of gb200-bmc.

Signed-off-by: Ed Tanous <etanous@nvidia.com>
---
 docs/system/arm/aspeed.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 43d27d83cb..bec0a1dfa8 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -1,5 +1,4 @@
-Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
-=================================================================================================================================================================================================================================================================================================================================================================================================================================
+Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
 
 The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
 Aspeed evaluation boards. They are based on different releases of the
@@ -35,6 +34,7 @@ AST2600 SoC based machines :
 - ``fuji-bmc``             Facebook Fuji BMC
 - ``bletchley-bmc``        Facebook Bletchley BMC
 - ``fby35-bmc``            Facebook fby35 BMC
+- ``gb200nvl-bmc``         Nvidia GB200nvl BMC
 - ``qcom-dc-scm-v1-bmc``   Qualcomm DC-SCM V1 BMC
 - ``qcom-firework-bmc``    Qualcomm Firework BMC
 
-- 
2.43.0

Re: [PATCH 3/4] docs: add support for gb200-bmc

[Cédric Le Goater]

On 7/1/25 22:33, Ed Tanous wrote:
> This patch updates the docs for support of gb200-bmc.
> 
> Signed-off-by: Ed Tanous <etanous@nvidia.com>
> ---
>   docs/system/arm/aspeed.rst | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
> index 43d27d83cb..bec0a1dfa8 100644
> --- a/docs/system/arm/aspeed.rst
> +++ b/docs/system/arm/aspeed.rst
> @@ -1,5 +1,4 @@
> -Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
> -=================================================================================================================================================================================================================================================================================================================================================================================================================================
> +Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
>   
>   The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
>   Aspeed evaluation boards. They are based on different releases of the
> @@ -35,6 +34,7 @@ AST2600 SoC based machines :
>   - ``fuji-bmc``             Facebook Fuji BMC
>   - ``bletchley-bmc``        Facebook Bletchley BMC
>   - ``fby35-bmc``            Facebook fby35 BMC
> +- ``gb200nvl-bmc``         Nvidia GB200nvl BMC
>   - ``qcom-dc-scm-v1-bmc``   Qualcomm DC-SCM V1 BMC
>   - ``qcom-firework-bmc``    Qualcomm Firework BMC
>   


Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.

[PATCH 4/4] hw/arm/aspeed: Add GB200 BMC target

[Ed Tanous]

GB200nvl72 is a system for for accelerated compute.  This is a model for
the BMC target within the system.

Signed-off-by: Ed Tanous <etanous@nvidia.com>
---
 hw/arm/aspeed.c        | 79 ++++++++++++++++++++++++++++++++++++++++++
 hw/arm/aspeed_eeprom.c | 21 +++++++++++
 hw/arm/aspeed_eeprom.h |  3 ++
 3 files changed, 103 insertions(+)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 3ef7f6c5b2..98144ced86 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -19,6 +19,7 @@
 #include "hw/i2c/i2c_mux_pca954x.h"
 #include "hw/i2c/smbus_eeprom.h"
 #include "hw/gpio/pca9552.h"
+#include "hw/gpio/pca9554.h"
 #include "hw/nvram/eeprom_at24c.h"
 #include "hw/sensor/tmp105.h"
 #include "hw/misc/led.h"
@@ -201,6 +202,10 @@ struct AspeedMachineState {
 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
 
+/* GB200NVL hardware value */
+#define GB200NVL_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
+#define GB200NVL_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
+
 /* Qualcomm DC-SCM hardware value */
 #define QCOM_DC_SCM_V1_BMC_HW_STRAP1  0x00000000
 #define QCOM_DC_SCM_V1_BMC_HW_STRAP2  0x00000041
@@ -647,6 +652,12 @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
                             TYPE_PCA9552, addr);
 }
 
+static I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr)
+{
+    return i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
+                            TYPE_PCA9554, addr);
+}
+
 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
 {
     AspeedSoCState *soc = bmc->soc;
@@ -1052,6 +1063,45 @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
     i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
 }
 
+
+static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc)
+{
+    AspeedSoCState *soc = bmc->soc;
+    I2CBus *i2c[15] = {};
+    DeviceState *dev;
+    for (int i = 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) {
+        if ((i == 11) || (i == 12) || (i == 13)) {
+            continue;
+        }
+        i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
+    }
+
+    /* Bus 5 Expander */
+    create_pca9554(soc, 4, 0x21);
+
+    /* Mux I2c Expanders */
+    i2c_slave_create_simple(i2c[5], "pca9546", 0x71);
+    i2c_slave_create_simple(i2c[5], "pca9546", 0x72);
+    i2c_slave_create_simple(i2c[5], "pca9546", 0x73);
+    i2c_slave_create_simple(i2c[5], "pca9546", 0x75);
+    i2c_slave_create_simple(i2c[5], "pca9546", 0x76);
+    i2c_slave_create_simple(i2c[5], "pca9546", 0x77);
+
+    /* Bus 10 */
+    dev = DEVICE(create_pca9554(soc, 9, 0x20));
+
+    /* Set FPGA_READY */
+    object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal);
+
+    create_pca9554(soc, 9, 0x21);
+    at24c_eeprom_init(i2c[9], 0x50, 64 * KiB);
+    at24c_eeprom_init(i2c[9], 0x51, 64 * KiB);
+
+    /* Bus 11 */
+    at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid,
+                          gb200nvl_bmc_fruid_len);
+}
+
 static void fby35_i2c_init(AspeedMachineState *bmc)
 {
     AspeedSoCState *soc = bmc->soc;
@@ -1587,6 +1637,31 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc,
     aspeed_machine_class_init_cpus_defaults(mc);
 }
 
+#define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB)
+
+static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc,
+                                               const void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+    mc->desc       = "Nvidia GB200NVL BMC (Cortex-A7)";
+    amc->soc_name  = "ast2600-a3";
+    amc->hw_strap1 = GB200NVL_BMC_HW_STRAP1;
+    amc->hw_strap2 = GB200NVL_BMC_HW_STRAP2;
+    amc->fmc_model = "mx66u51235f";
+    amc->spi_model = "mx66u51235f";
+    amc->num_cs    = 2;
+
+    amc->spi2_model = "mx66u51235f";
+    amc->num_cs2   = 1;
+    amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
+    amc->i2c_init  = gb200nvl_bmc_i2c_init;
+    mc->default_ram_size = GB200NVL_BMC_RAM_SIZE;
+    aspeed_machine_class_init_cpus_defaults(mc);
+    aspeed_machine_ast2600_class_emmc_init(oc);
+}
+
 static void fby35_reset(MachineState *state, ResetType type)
 {
     AspeedMachineState *bmc = ASPEED_MACHINE(state);
@@ -1879,6 +1954,10 @@ static const TypeInfo aspeed_machine_types[] = {
         .name          = MACHINE_TYPE_NAME("bletchley-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_bletchley_class_init,
+    }, {
+        .name          = MACHINE_TYPE_NAME("gb200nvl-bmc"),
+        .parent        = TYPE_ASPEED_MACHINE,
+        .class_init    = aspeed_machine_gb200nvl_class_init,
     }, {
         .name          = MACHINE_TYPE_NAME("fby35-bmc"),
         .parent        = MACHINE_TYPE_NAME("ast2600-evb"),
diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c
index daa3d329d1..8bbbdec834 100644
--- a/hw/arm/aspeed_eeprom.c
+++ b/hw/arm/aspeed_eeprom.c
@@ -162,6 +162,25 @@ const uint8_t rainier_bmc_fruid[] = {
     0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
 };
 
+const uint8_t gb200nvl_bmc_fruid[] = {
+    0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, 0x19, 0x1f,
+    0x0f, 0xe6, 0xc6, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0xc5, 0x50, 0x33,
+    0x38, 0x30, 0x39, 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38,
+    0x30, 0x30, 0x31, 0x35, 0x30, 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33,
+    0x38, 0x30, 0x39, 0x2d, 0x30, 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30,
+    0xc0, 0x01, 0x01, 0xd6, 0x4d, 0x41, 0x43, 0x3a, 0x20, 0x33, 0x43, 0x3a,
+    0x36, 0x44, 0x3a, 0x36, 0x36, 0x3a, 0x31, 0x34, 0x3a, 0x43, 0x38, 0x3a,
+    0x37, 0x41, 0xc1, 0x3b, 0x01, 0x09, 0x19, 0xc6, 0x4e, 0x56, 0x49, 0x44,
+    0x49, 0x41, 0xc9, 0x50, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x42, 0x4d, 0x43,
+    0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x30,
+    0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, 0xc4, 0x41, 0x45, 0x2e, 0x31,
+    0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, 0x30, 0x30, 0x31,
+    0x35, 0x30, 0xc0, 0xc4, 0x76, 0x30, 0x2e, 0x31, 0xc1, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0xb4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+
+};
+
 const size_t tiogapass_bmc_fruid_len = sizeof(tiogapass_bmc_fruid);
 const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid);
 const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid);
@@ -169,3 +188,5 @@ const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid);
 const size_t yosemitev2_bmc_fruid_len = sizeof(yosemitev2_bmc_fruid);
 const size_t rainier_bb_fruid_len = sizeof(rainier_bb_fruid);
 const size_t rainier_bmc_fruid_len = sizeof(rainier_bmc_fruid);
+const size_t gb200nvl_bmc_fruid_len = sizeof(gb200nvl_bmc_fruid);
+
diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h
index f08c16ef50..3ed9bc1d9a 100644
--- a/hw/arm/aspeed_eeprom.h
+++ b/hw/arm/aspeed_eeprom.h
@@ -26,4 +26,7 @@ extern const size_t rainier_bb_fruid_len;
 extern const uint8_t rainier_bmc_fruid[];
 extern const size_t rainier_bmc_fruid_len;
 
+extern const uint8_t gb200nvl_bmc_fruid[];
+extern const size_t gb200nvl_bmc_fruid_len;
+
 #endif
-- 
2.43.0

Re: [PATCH 4/4] hw/arm/aspeed: Add GB200 BMC target

[Cédric Le Goater]

On 7/1/25 22:34, Ed Tanous wrote:
> GB200nvl72 is a system for for accelerated compute.  This is a model for
> the BMC target within the system.

Could you please add a comment saying it is based on DT :

   aspeed-bmc-nvidia-gb200nvl-bmc.dts

from

   https://github.com/openbmc/linux/blob/dev-6.6/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts


> Signed-off-by: Ed Tanous <etanous@nvidia.com>
> ---
>   hw/arm/aspeed.c        | 79 ++++++++++++++++++++++++++++++++++++++++++
>   hw/arm/aspeed_eeprom.c | 21 +++++++++++
>   hw/arm/aspeed_eeprom.h |  3 ++
>   3 files changed, 103 insertions(+)
> 
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 3ef7f6c5b2..98144ced86 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -19,6 +19,7 @@
>   #include "hw/i2c/i2c_mux_pca954x.h"
>   #include "hw/i2c/smbus_eeprom.h"
>   #include "hw/gpio/pca9552.h"
> +#include "hw/gpio/pca9554.h"
>   #include "hw/nvram/eeprom_at24c.h"
>   #include "hw/sensor/tmp105.h"
>   #include "hw/misc/led.h"
> @@ -201,6 +202,10 @@ struct AspeedMachineState {
>   #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
>   #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
>   
> +/* GB200NVL hardware value */
> +#define GB200NVL_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
> +#define GB200NVL_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
> +
>   /* Qualcomm DC-SCM hardware value */
>   #define QCOM_DC_SCM_V1_BMC_HW_STRAP1  0x00000000
>   #define QCOM_DC_SCM_V1_BMC_HW_STRAP2  0x00000041
> @@ -647,6 +652,12 @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
>                               TYPE_PCA9552, addr);
>   }
>   
> +static I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr)
> +{
> +    return i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
> +                            TYPE_PCA9554, addr);
> +}
> +
>   static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
>   {
>       AspeedSoCState *soc = bmc->soc;
> @@ -1052,6 +1063,45 @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
>       i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
>   }
>   
> +> +static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc)
> +{
> +    AspeedSoCState *soc = bmc->soc;
> +    I2CBus *i2c[15] = {};
> +    DeviceState *dev;
> +    for (int i = 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) {
> +        if ((i == 11) || (i == 12) || (i == 13)) {
> +            continue;
> +        }
> +        i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
> +    }
> +
> +    /* Bus 5 Expander */
> +    create_pca9554(soc, 4, 0x21);
> +
> +    /* Mux I2c Expanders */
> +    i2c_slave_create_simple(i2c[5], "pca9546", 0x71);
> +    i2c_slave_create_simple(i2c[5], "pca9546", 0x72);
> +    i2c_slave_create_simple(i2c[5], "pca9546", 0x73);
> +    i2c_slave_create_simple(i2c[5], "pca9546", 0x75);
> +    i2c_slave_create_simple(i2c[5], "pca9546", 0x76);
> +    i2c_slave_create_simple(i2c[5], "pca9546", 0x77);
> +
> +    /* Bus 10 */
> +    dev = DEVICE(create_pca9554(soc, 9, 0x20));
> +
> +    /* Set FPGA_READY */
> +    object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal);
> +
> +    create_pca9554(soc, 9, 0x21);
> +    at24c_eeprom_init(i2c[9], 0x50, 64 * KiB);
> +    at24c_eeprom_init(i2c[9], 0x51, 64 * KiB);
> +
> +    /* Bus 11 */
> +    at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid,
> +                          gb200nvl_bmc_fruid_len);
> +}
> +
>   static void fby35_i2c_init(AspeedMachineState *bmc)
>   {
>       AspeedSoCState *soc = bmc->soc;
> @@ -1587,6 +1637,31 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc,
>       aspeed_machine_class_init_cpus_defaults(mc);
>   }
>   
> +#define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB)
> +
> +static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc,
> +                                               const void *data)
> +{
> +    MachineClass *mc = MACHINE_CLASS(oc);
> +    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
> +
> +    mc->desc       = "Nvidia GB200NVL BMC (Cortex-A7)";
> +    amc->soc_name  = "ast2600-a3";
> +    amc->hw_strap1 = GB200NVL_BMC_HW_STRAP1;
> +    amc->hw_strap2 = GB200NVL_BMC_HW_STRAP2;
> +    amc->fmc_model = "mx66u51235f";
> +    amc->spi_model = "mx66u51235f";
> +    amc->num_cs    = 2;
> +
> +    amc->spi2_model = "mx66u51235f";
> +    amc->num_cs2   = 1;
> +    amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> +    amc->i2c_init  = gb200nvl_bmc_i2c_init;
> +    mc->default_ram_size = GB200NVL_BMC_RAM_SIZE;
> +    aspeed_machine_class_init_cpus_defaults(mc);
> +    aspeed_machine_ast2600_class_emmc_init(oc);
> +}
> +
>   static void fby35_reset(MachineState *state, ResetType type)
>   {
>       AspeedMachineState *bmc = ASPEED_MACHINE(state);
> @@ -1879,6 +1954,10 @@ static const TypeInfo aspeed_machine_types[] = {
>           .name          = MACHINE_TYPE_NAME("bletchley-bmc"),
>           .parent        = TYPE_ASPEED_MACHINE,
>           .class_init    = aspeed_machine_bletchley_class_init,
> +    }, {
> +        .name          = MACHINE_TYPE_NAME("gb200nvl-bmc"),
> +        .parent        = TYPE_ASPEED_MACHINE,
> +        .class_init    = aspeed_machine_gb200nvl_class_init,
>       }, {
>           .name          = MACHINE_TYPE_NAME("fby35-bmc"),
>           .parent        = MACHINE_TYPE_NAME("ast2600-evb"),
> diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c
> index daa3d329d1..8bbbdec834 100644
> --- a/hw/arm/aspeed_eeprom.c
> +++ b/hw/arm/aspeed_eeprom.c
> @@ -162,6 +162,25 @@ const uint8_t rainier_bmc_fruid[] = {
>       0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
>   };
>   
> +const uint8_t gb200nvl_bmc_fruid[] = {
> +    0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, 0x19, 0x1f,
> +    0x0f, 0xe6, 0xc6, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0xc5, 0x50, 0x33,
> +    0x38, 0x30, 0x39, 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38,
> +    0x30, 0x30, 0x31, 0x35, 0x30, 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33,
> +    0x38, 0x30, 0x39, 0x2d, 0x30, 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30,
> +    0xc0, 0x01, 0x01, 0xd6, 0x4d, 0x41, 0x43, 0x3a, 0x20, 0x33, 0x43, 0x3a,
> +    0x36, 0x44, 0x3a, 0x36, 0x36, 0x3a, 0x31, 0x34, 0x3a, 0x43, 0x38, 0x3a,
> +    0x37, 0x41, 0xc1, 0x3b, 0x01, 0x09, 0x19, 0xc6, 0x4e, 0x56, 0x49, 0x44,
> +    0x49, 0x41, 0xc9, 0x50, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x42, 0x4d, 0x43,
> +    0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x30,
> +    0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, 0xc4, 0x41, 0x45, 0x2e, 0x31,
> +    0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, 0x30, 0x30, 0x31,
> +    0x35, 0x30, 0xc0, 0xc4, 0x76, 0x30, 0x2e, 0x31, 0xc1, 0x00, 0x00, 0x00,
> +    0x00, 0x00, 0x00, 0xb4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
> +
> +};
> +
>   const size_t tiogapass_bmc_fruid_len = sizeof(tiogapass_bmc_fruid);
>   const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid);
>   const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid);
> @@ -169,3 +188,5 @@ const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid);
>   const size_t yosemitev2_bmc_fruid_len = sizeof(yosemitev2_bmc_fruid);
>   const size_t rainier_bb_fruid_len = sizeof(rainier_bb_fruid);
>   const size_t rainier_bmc_fruid_len = sizeof(rainier_bmc_fruid);
> +const size_t gb200nvl_bmc_fruid_len = sizeof(gb200nvl_bmc_fruid);
> +
> diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h
> index f08c16ef50..3ed9bc1d9a 100644
> --- a/hw/arm/aspeed_eeprom.h
> +++ b/hw/arm/aspeed_eeprom.h
> @@ -26,4 +26,7 @@ extern const size_t rainier_bb_fruid_len;
>   extern const uint8_t rainier_bmc_fruid[];
>   extern const size_t rainier_bmc_fruid_len;
>   
> +extern const uint8_t gb200nvl_bmc_fruid[];
> +extern const size_t gb200nvl_bmc_fruid_len;
> +
>   #endif

Re: [PATCH 4/4] hw/arm/aspeed: Add GB200 BMC target

[Ed Tanous via]

On Wed, Jul 02, 2025 at 11:38:53PM +0200, Cédric Le Goater wrote:
> On 7/1/25 22:34, Ed Tanous wrote:
> > GB200nvl72 is a system for for accelerated compute.  This is a model for
> > the BMC target within the system.
> 
> Could you please add a comment saying it is based on DT :
> 
>   aspeed-bmc-nvidia-gb200nvl-bmc.dts
> 
> from
> 
>   https://github.com/openbmc/linux/blob/dev-6.6/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts
> 

ACK.  Will add to the commit message in v2.

> 
> > Signed-off-by: Ed Tanous <etanous@nvidia.com>
> > ---
> >   hw/arm/aspeed.c        | 79 ++++++++++++++++++++++++++++++++++++++++++
> >   hw/arm/aspeed_eeprom.c | 21 +++++++++++
> >   hw/arm/aspeed_eeprom.h |  3 ++
> >   3 files changed, 103 insertions(+)
> > 
> > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> > index 3ef7f6c5b2..98144ced86 100644
> > --- a/hw/arm/aspeed.c
> > +++ b/hw/arm/aspeed.c
> > @@ -19,6 +19,7 @@
> >   #include "hw/i2c/i2c_mux_pca954x.h"
> >   #include "hw/i2c/smbus_eeprom.h"
> >   #include "hw/gpio/pca9552.h"
> > +#include "hw/gpio/pca9554.h"
> >   #include "hw/nvram/eeprom_at24c.h"
> >   #include "hw/sensor/tmp105.h"
> >   #include "hw/misc/led.h"
> > @@ -201,6 +202,10 @@ struct AspeedMachineState {
> >   #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
> >   #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
> > +/* GB200NVL hardware value */
> > +#define GB200NVL_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
> > +#define GB200NVL_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
> > +
> >   /* Qualcomm DC-SCM hardware value */
> >   #define QCOM_DC_SCM_V1_BMC_HW_STRAP1  0x00000000
> >   #define QCOM_DC_SCM_V1_BMC_HW_STRAP2  0x00000041
> > @@ -647,6 +652,12 @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
> >                               TYPE_PCA9552, addr);
> >   }
> > +static I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr)
> > +{
> > +    return i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
> > +                            TYPE_PCA9554, addr);
> > +}
> > +
> >   static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
> >   {
> >       AspeedSoCState *soc = bmc->soc;
> > @@ -1052,6 +1063,45 @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
> >       i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
> >   }
> > +> +static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc)
> > +{
> > +    AspeedSoCState *soc = bmc->soc;
> > +    I2CBus *i2c[15] = {};
> > +    DeviceState *dev;
> > +    for (int i = 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) {
> > +        if ((i == 11) || (i == 12) || (i == 13)) {
> > +            continue;
> > +        }
> > +        i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
> > +    }
> > +
> > +    /* Bus 5 Expander */
> > +    create_pca9554(soc, 4, 0x21);
> > +
> > +    /* Mux I2c Expanders */
> > +    i2c_slave_create_simple(i2c[5], "pca9546", 0x71);
> > +    i2c_slave_create_simple(i2c[5], "pca9546", 0x72);
> > +    i2c_slave_create_simple(i2c[5], "pca9546", 0x73);
> > +    i2c_slave_create_simple(i2c[5], "pca9546", 0x75);
> > +    i2c_slave_create_simple(i2c[5], "pca9546", 0x76);
> > +    i2c_slave_create_simple(i2c[5], "pca9546", 0x77);
> > +
> > +    /* Bus 10 */
> > +    dev = DEVICE(create_pca9554(soc, 9, 0x20));
> > +
> > +    /* Set FPGA_READY */
> > +    object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal);
> > +
> > +    create_pca9554(soc, 9, 0x21);
> > +    at24c_eeprom_init(i2c[9], 0x50, 64 * KiB);
> > +    at24c_eeprom_init(i2c[9], 0x51, 64 * KiB);
> > +
> > +    /* Bus 11 */
> > +    at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid,
> > +                          gb200nvl_bmc_fruid_len);
> > +}
> > +
> >   static void fby35_i2c_init(AspeedMachineState *bmc)
> >   {
> >       AspeedSoCState *soc = bmc->soc;
> > @@ -1587,6 +1637,31 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc,
> >       aspeed_machine_class_init_cpus_defaults(mc);
> >   }
> > +#define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB)
> > +
> > +static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc,
> > +                                               const void *data)
> > +{
> > +    MachineClass *mc = MACHINE_CLASS(oc);
> > +    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
> > +
> > +    mc->desc       = "Nvidia GB200NVL BMC (Cortex-A7)";
> > +    amc->soc_name  = "ast2600-a3";
> > +    amc->hw_strap1 = GB200NVL_BMC_HW_STRAP1;
> > +    amc->hw_strap2 = GB200NVL_BMC_HW_STRAP2;
> > +    amc->fmc_model = "mx66u51235f";
> > +    amc->spi_model = "mx66u51235f";
> > +    amc->num_cs    = 2;
> > +
> > +    amc->spi2_model = "mx66u51235f";
> > +    amc->num_cs2   = 1;
> > +    amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> > +    amc->i2c_init  = gb200nvl_bmc_i2c_init;
> > +    mc->default_ram_size = GB200NVL_BMC_RAM_SIZE;
> > +    aspeed_machine_class_init_cpus_defaults(mc);
> > +    aspeed_machine_ast2600_class_emmc_init(oc);
> > +}
> > +
> >   static void fby35_reset(MachineState *state, ResetType type)
> >   {
> >       AspeedMachineState *bmc = ASPEED_MACHINE(state);
> > @@ -1879,6 +1954,10 @@ static const TypeInfo aspeed_machine_types[] = {
> >           .name          = MACHINE_TYPE_NAME("bletchley-bmc"),
> >           .parent        = TYPE_ASPEED_MACHINE,
> >           .class_init    = aspeed_machine_bletchley_class_init,
> > +    }, {
> > +        .name          = MACHINE_TYPE_NAME("gb200nvl-bmc"),
> > +        .parent        = TYPE_ASPEED_MACHINE,
> > +        .class_init    = aspeed_machine_gb200nvl_class_init,
> >       }, {
> >           .name          = MACHINE_TYPE_NAME("fby35-bmc"),
> >           .parent        = MACHINE_TYPE_NAME("ast2600-evb"),
> > diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c
> > index daa3d329d1..8bbbdec834 100644
> > --- a/hw/arm/aspeed_eeprom.c
> > +++ b/hw/arm/aspeed_eeprom.c
> > @@ -162,6 +162,25 @@ const uint8_t rainier_bmc_fruid[] = {
> >       0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
> >   };
> > +const uint8_t gb200nvl_bmc_fruid[] = {
> > +    0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, 0x19, 0x1f,
> > +    0x0f, 0xe6, 0xc6, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0xc5, 0x50, 0x33,
> > +    0x38, 0x30, 0x39, 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38,
> > +    0x30, 0x30, 0x31, 0x35, 0x30, 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33,
> > +    0x38, 0x30, 0x39, 0x2d, 0x30, 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30,
> > +    0xc0, 0x01, 0x01, 0xd6, 0x4d, 0x41, 0x43, 0x3a, 0x20, 0x33, 0x43, 0x3a,
> > +    0x36, 0x44, 0x3a, 0x36, 0x36, 0x3a, 0x31, 0x34, 0x3a, 0x43, 0x38, 0x3a,
> > +    0x37, 0x41, 0xc1, 0x3b, 0x01, 0x09, 0x19, 0xc6, 0x4e, 0x56, 0x49, 0x44,
> > +    0x49, 0x41, 0xc9, 0x50, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x42, 0x4d, 0x43,
> > +    0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x30,
> > +    0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, 0xc4, 0x41, 0x45, 0x2e, 0x31,
> > +    0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, 0x30, 0x30, 0x31,
> > +    0x35, 0x30, 0xc0, 0xc4, 0x76, 0x30, 0x2e, 0x31, 0xc1, 0x00, 0x00, 0x00,
> > +    0x00, 0x00, 0x00, 0xb4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> > +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
> > +
> > +};
> > +
> >   const size_t tiogapass_bmc_fruid_len = sizeof(tiogapass_bmc_fruid);
> >   const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid);
> >   const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid);
> > @@ -169,3 +188,5 @@ const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid);
> >   const size_t yosemitev2_bmc_fruid_len = sizeof(yosemitev2_bmc_fruid);
> >   const size_t rainier_bb_fruid_len = sizeof(rainier_bb_fruid);
> >   const size_t rainier_bmc_fruid_len = sizeof(rainier_bmc_fruid);
> > +const size_t gb200nvl_bmc_fruid_len = sizeof(gb200nvl_bmc_fruid);
> > +
> > diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h
> > index f08c16ef50..3ed9bc1d9a 100644
> > --- a/hw/arm/aspeed_eeprom.h
> > +++ b/hw/arm/aspeed_eeprom.h
> > @@ -26,4 +26,7 @@ extern const size_t rainier_bb_fruid_len;
> >   extern const uint8_t rainier_bmc_fruid[];
> >   extern const size_t rainier_bmc_fruid_len;
> > +extern const uint8_t gb200nvl_bmc_fruid[];
> > +extern const size_t gb200nvl_bmc_fruid_len;
> > +
> >   #endif
> 

Re: [PATCH 0/4] Add support for gb200-bmc machine

[Cédric Le Goater]

On 7/1/25 22:33, Ed Tanous wrote:
> This patch series adds support for gb200-bmc, a baseboard management controller
> module based on an Aspeed 2600 SOC.
> 
> Ed Tanous (4):
>    hw/arm: Add PCA9554 to ARM target
>    hw/arm/aspeed: Add second SPI chip to Aspeed model
>    docs: add support for gb200-bmc
>    hw/arm/aspeed: Add GB200 BMC target
> 
>   docs/system/arm/aspeed.rst |  4 +-
>   hw/arm/Kconfig             |  1 +
>   hw/arm/aspeed.c            | 81 ++++++++++++++++++++++++++++++++++++++
>   hw/arm/aspeed_eeprom.c     | 21 ++++++++++
>   hw/arm/aspeed_eeprom.h     |  3 ++
>   include/hw/arm/aspeed.h    |  2 +
>   6 files changed, 110 insertions(+), 2 deletions(-)
> 

Could you provide a functional test for the gb200nvl-bmc machine too ?
See tests/functional/test_*aspeed* files.

Thanks,

C.

Re: [PATCH 0/4] Add support for gb200-bmc machine

[etanous via]

On Wed, Jul 02, 2025 at 09:00:53AM +0200, Cédric Le Goater wrote:
> External email: Use caution opening links or attachments
> 
> 
> On 7/1/25 22:33, Ed Tanous wrote:
> > This patch series adds support for gb200-bmc, a baseboard management controller
> > module based on an Aspeed 2600 SOC.
> > 
> > Ed Tanous (4):
> >    hw/arm: Add PCA9554 to ARM target
> >    hw/arm/aspeed: Add second SPI chip to Aspeed model
> >    docs: add support for gb200-bmc
> >    hw/arm/aspeed: Add GB200 BMC target
> > 
> >   docs/system/arm/aspeed.rst |  4 +-
> >   hw/arm/Kconfig             |  1 +
> >   hw/arm/aspeed.c            | 81 ++++++++++++++++++++++++++++++++++++++
> >   hw/arm/aspeed_eeprom.c     | 21 ++++++++++
> >   hw/arm/aspeed_eeprom.h     |  3 ++
> >   include/hw/arm/aspeed.h    |  2 +
> >   6 files changed, 110 insertions(+), 2 deletions(-)
> > 
> 
> Could you provide a functional test for the gb200nvl-bmc machine too ?
> See tests/functional/test_*aspeed* files.
> 

Can do.  It looks like images are pushed to
https://github.com/legoater/qemu-aspeed-boot and accepted via Github PR?
Will open PR shortly.

> Thanks,
> 
> C.
> 
> 

Re: [PATCH 0/4] Add support for gb200-bmc machine

[Cédric Le Goater]

On 7/2/25 21:31, etanous wrote:
> On Wed, Jul 02, 2025 at 09:00:53AM +0200, Cédric Le Goater wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> On 7/1/25 22:33, Ed Tanous wrote:
>>> This patch series adds support for gb200-bmc, a baseboard management controller
>>> module based on an Aspeed 2600 SOC.
>>>
>>> Ed Tanous (4):
>>>     hw/arm: Add PCA9554 to ARM target
>>>     hw/arm/aspeed: Add second SPI chip to Aspeed model
>>>     docs: add support for gb200-bmc
>>>     hw/arm/aspeed: Add GB200 BMC target
>>>
>>>    docs/system/arm/aspeed.rst |  4 +-
>>>    hw/arm/Kconfig             |  1 +
>>>    hw/arm/aspeed.c            | 81 ++++++++++++++++++++++++++++++++++++++
>>>    hw/arm/aspeed_eeprom.c     | 21 ++++++++++
>>>    hw/arm/aspeed_eeprom.h     |  3 ++
>>>    include/hw/arm/aspeed.h    |  2 +
>>>    6 files changed, 110 insertions(+), 2 deletions(-)
>>>
>>
>> Could you provide a functional test for the gb200nvl-bmc machine too ?
>> See tests/functional/test_*aspeed* files.
>>
> 
> Can do.  It looks like images are pushed to
> https://github.com/legoater/qemu-aspeed-boot and accepted via Github PR?

Yes. please do that. It seems the easiest way to collect FW images.

Please provide some info on how it was built, openbmc version, repo, etc.

Thanks,

C.