From: Zhao Liu <zhao1.liu@intel.com>
To: Xiaoyao Li <xiaoyao.li@intel.com>
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Dongli Zhang" <dongli.zhang@oracle.com>,
"Thomas Huth" <thuth@redhat.com>,
qemu-devel <qemu-devel@nongnu.org>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Like Xu" <like.xu.linux@gmail.com>,
"Igor Mammedov" <imammedo@redhat.com>
Subject: Re: [Regression] Re: [PULL 35/35] qom: reverse order of instance_post_init calls
Date: Thu, 3 Jul 2025 11:08:18 +0800 [thread overview]
Message-ID: <aGX0Im2F6R4nTUh4@intel.com> (raw)
In-Reply-To: <a7d2691b-ce43-454e-aec9-3589787dea5c@intel.com>
On Thu, Jul 03, 2025 at 09:03:10AM +0800, Xiaoyao Li wrote:
> Date: Thu, 3 Jul 2025 09:03:10 +0800
> From: Xiaoyao Li <xiaoyao.li@intel.com>
> Subject: Re: [Regression] Re: [PULL 35/35] qom: reverse order of
> instance_post_init calls
>
> On 7/3/2025 2:54 AM, Paolo Bonzini wrote:
> > Il mer 2 lug 2025, 09:25 Xiaoyao Li <xiaoyao.li@intel.com> ha scritto:
> >
> > > IIRC that's on rhel QEMU which ports the TDX code before it's merged
> > > upstream. Now TDX is upstreamed, it works with upstream compat property
> > > and I think future new compat property won't affect TDX or anything,
> > > since it's compat property and it's to guarantee the existing behavior
> > > when introducing new behavior?
> > >
> >
> > It's a compat property that is only added by RHEL-specific machine types.
> > But the bug is not specific to RHEL, it just happens that no upstream
> > machine type has compat properties that overlap with TDX adjustments of
> > CPUID.
> >
> > > In general I don't see how the reverse order makes sense: the subclass
> > > > knows what the superclass does, so it can do the right thing if it runs
> > > > last; but the superclass cannot know what all of its subclasses do in
> > > > post_init, so it makes less sense to run it last.
> > >
> > > I agree in general the parent to child order makes more sense,
> > > especially when we treat .instance_init() as the phase 1 init and
> > > .post_instance_init() as the phase 2 init.
> > >
> > > But the original purpose of introducing .post_instance_init() was to
> > > ensure qdev_prop_set_globals() is called at last for Device. Reverse the
> > > order breaks this purpose.
> > >
> >
> > Not "last", but "after instance_init". Anything that happens in the child
> > class's instance_post_init can be moved at the end of instance_init, just
> > like the refactoring that I did for risc-v.
>
> Move into the end of instance_init() can surely work. But it requires to
> split the code in instance_post_init() to different child's instance_init()
> or making sure the code in instance_post_init() is called at the end of each
> lowest child class.
Initially, when I proposed the split approach, it wasn't about
splitting for the sake of splitting, nor for the sake of "work".
A more granular split is just a means, and the goal is to place things
at different stages in the most appropriate locations.
> Besides, it also leads to a rule that child of Device's
> .post_instance_init() needs to be careful about changing the property or
> anything that might affect the property,
I believe that's how things should be. instance_post_init() provides an
opportunity to tweak properties. The order of instance_post_init()
reflects the dependency relationships for property adjustments. As I
mentioned earlier, if a property doesn't need to consider other factors
and is simply being initialized, instance_init() is the most appropriate
place for it.
> because it might break the usage of global properties.
Breaking global properties is just one example. Essentially, properties
like "vendor" don't adhere well to the semantics of QOM.
> This can surely work. But to me, it seems to make code worse not better.
IMO, it's not the split that makes things worse, but rather the improper
use of instance_post_init() that makes everything about the x86 CPU
fragile. Ideally, QOM/qdev should focus on their own abstraction order,
while the leaf-class should do the right thing in the right place, which
is the most solid situation.
next prev parent reply other threads:[~2025-07-03 2:47 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-20 11:04 [PULL 00/35] RISCV, i386, endianness fixes for 2025-05-20 Paolo Bonzini
2025-05-20 11:04 ` [PULL 01/35] i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported Paolo Bonzini
2025-05-20 11:04 ` [PULL 02/35] i386/hvf: Make CPUID_HT supported Paolo Bonzini
2025-05-20 11:04 ` [PULL 03/35] hw/pci-host/gt64120: Fix endianness handling Paolo Bonzini
2025-05-20 11:04 ` [PULL 04/35] hw/pci-host: Remove unused pci_host_data_be_ops Paolo Bonzini
2025-05-20 11:05 ` [PULL 05/35] qapi/misc-target: Rename SGXEPCSection to SgxEpcSection Paolo Bonzini
2025-05-20 11:05 ` [PULL 06/35] qapi/misc-target: Rename SGXInfo to SgxInfo Paolo Bonzini
2025-05-20 11:05 ` [PULL 07/35] qapi/misc-target: Fix the doc related SGXEPCSection Paolo Bonzini
2025-05-20 11:05 ` [PULL 08/35] qapi/misc-target: Fix the doc to distinguish query-sgx and query-sgx-capabilities Paolo Bonzini
2025-05-20 11:05 ` [PULL 09/35] hw/riscv: acpi: only create RHCT MMU entry for supported types Paolo Bonzini
2025-05-20 11:05 ` [PULL 10/35] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-05-20 11:05 ` [PULL 11/35] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-05-20 11:05 ` [PULL 12/35] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-05-20 11:05 ` [PULL 13/35] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-05-20 11:05 ` [PULL 14/35] target/riscv: move satp_mode.{map, init} out of CPUConfig Paolo Bonzini via
2025-05-20 11:05 ` [PULL 15/35] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-05-20 11:05 ` [PULL 16/35] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-05-20 11:05 ` [PULL 17/35] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-05-20 11:05 ` [PULL 18/35] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-05-20 11:05 ` [PULL 19/35] target/riscv: include default value in cpu_cfg_fields.h.inc Paolo Bonzini
2025-05-20 11:05 ` [PULL 20/35] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-05-20 11:05 ` [PULL 21/35] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-05-20 11:05 ` [PULL 22/35] target/riscv: convert profile CPU models " Paolo Bonzini
2025-05-20 11:05 ` [PULL 23/35] target/riscv: convert bare " Paolo Bonzini
2025-05-20 11:05 ` [PULL 24/35] target/riscv: convert dynamic " Paolo Bonzini
2025-05-20 11:05 ` [PULL 25/35] target/riscv: convert SiFive E " Paolo Bonzini
2025-05-20 11:05 ` [PULL 26/35] target/riscv: convert ibex " Paolo Bonzini
2025-05-20 11:05 ` [PULL 27/35] target/riscv: convert SiFive U " Paolo Bonzini
2025-05-20 11:05 ` [PULL 28/35] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-05-20 11:05 ` [PULL 29/35] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-05-20 11:05 ` [PULL 30/35] target/riscv: convert THead C906 to RISCVCPUDef Paolo Bonzini
2025-05-20 11:05 ` [PULL 31/35] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-05-20 11:05 ` [PULL 32/35] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-05-20 11:05 ` [PULL 33/35] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-05-20 11:05 ` [PULL 34/35] target/riscv: remove .instance_post_init Paolo Bonzini
2025-05-20 11:05 ` [PULL 35/35] qom: reverse order of instance_post_init calls Paolo Bonzini
2025-06-23 16:56 ` [Regression] " Dongli Zhang
2025-06-24 8:57 ` Zhao Liu
2025-06-30 15:22 ` Zhao Liu
2025-07-01 6:50 ` Xiaoyao Li
2025-07-02 6:54 ` Philippe Mathieu-Daudé
2025-07-02 7:56 ` Zhao Liu
2025-07-02 11:42 ` Xiaoyao Li
2025-07-02 12:12 ` Paolo Bonzini
2025-07-02 13:24 ` Xiaoyao Li
2025-07-02 18:54 ` Paolo Bonzini
2025-07-03 1:03 ` Xiaoyao Li
2025-07-03 3:08 ` Zhao Liu [this message]
2025-07-03 3:36 ` Xiaoyao Li
2025-07-03 4:51 ` Paolo Bonzini
2025-07-07 15:41 ` Paolo Bonzini
2025-07-02 12:06 ` Paolo Bonzini
2025-05-21 14:06 ` [PULL 00/35] RISCV, i386, endianness fixes for 2025-05-20 Stefan Hajnoczi
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