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Wed, 16 Jul 2025 11:17:09 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 16 Jul 2025 11:17:08 -0700 Received: from Asurada-Nvidia (10.127.8.10) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14 via Frontend Transport; Wed, 16 Jul 2025 11:17:08 -0700 Date: Wed, 16 Jul 2025 11:17:06 -0700 From: Nicolin Chen To: Shameerali Kolothum Thodi CC: "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "eric.auger@redhat.com" , "peter.maydell@linaro.org" , "jgg@nvidia.com" , "ddutile@redhat.com" , "berrange@redhat.com" , "nathanc@nvidia.com" , "mochs@nvidia.com" , "smostafa@google.com" , Linuxarm , "Wangzhou (B)" , jiangkunkun , Jonathan Cameron , "zhangfei.gao@linaro.org" , "zhenzhong.duan@intel.com" , "shameerkolothum@gmail.com" Subject: Re: [RFC PATCH v3 09/15] hw/arm/smmuv3-accel: Support nested STE install/uninstall support Message-ID: References: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> <20250714155941.22176-10-shameerali.kolothum.thodi@huawei.com> <6110ab250e844af9982dddb230fb8707@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700013)(1800799024)(7416014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2025 18:17:26.8030 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 334e9a42-f5d9-4588-86e3-08ddc49504fa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8320 Received-SPF: permerror client-ip=2a01:111:f403:2417::616; envelope-from=nicolinc@nvidia.com; helo=NAM12-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Jul 16, 2025 at 08:36:38AM +0000, Shameerali Kolothum Thodi wrote: > > > + g_hash_table_foreach(bs->configs, smmuv3_accel_ste_range, range); > > > > This will not work correctly? > > > > The bs->configs is a cache that gets an entry inserted to when a > > config is fetched via smmuv3_get_config(), which gets invoked by > > smmuv3_notify_iova() and smmuv3_translate() only. > > > > But CMDQ_OP_CFGI_ALL can actually happen very early, e.g. Linux > > driver does that in the probe() right after SMMU CMDQ is enabled, > > at which point neither smmuv3_notify_iova nor smmuv3_translate > > could ever get invoked, meaning that the g_hash_table is empty. > > > > Without the acceleration, this foreach works because vSMMU does > > not need to do anything since the cache is indeed empty. > > > > But, with accel, it must call smmuv3_accel_install_nested_ste(). > > Ok. The only place I can see CMDQ_OP_CFGI_ALL get invoked by Linux > kernel is during arm_smmu_device_reset() and that is to clear all. > But I am not sure we will have any valid STEs at that time. Just curious, > are you seeing any issues with this at the moment? I recall that (not for this series) I hit some issue with a guest having "iommu.passthrough=y" string in its bootcmd. The guest OS initialized all SIDs to a Config.Bypass mode accordingly. But that was not handled correctly by QEMU so the host was not getting any request to program a stage-1 bypass STE to the HW. So, I think there would be a similar issue here. Nicolin