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Wed, 16 Jul 2025 11:37:24 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Wed, 16 Jul 2025 11:37:24 -0700 Received: from Asurada-Nvidia (10.127.8.10) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14 via Frontend Transport; Wed, 16 Jul 2025 11:37:23 -0700 Date: Wed, 16 Jul 2025 11:37:21 -0700 From: Nicolin Chen To: Shameerali Kolothum Thodi CC: "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "eric.auger@redhat.com" , "peter.maydell@linaro.org" , "jgg@nvidia.com" , "ddutile@redhat.com" , "berrange@redhat.com" , "nathanc@nvidia.com" , "mochs@nvidia.com" , "smostafa@google.com" , Linuxarm , "Wangzhou (B)" , jiangkunkun , Jonathan Cameron , "zhangfei.gao@linaro.org" , "zhenzhong.duan@intel.com" , "shameerkolothum@gmail.com" Subject: Re: [RFC PATCH v3 14/15] Read and validate host SMMUv3 feature bits Message-ID: References: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> <20250714155941.22176-15-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(7416014)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2025 18:37:36.9798 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4115697e-3b9b-4d51-20dd-08ddc497d651 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017091.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6652 Received-SPF: permerror client-ip=2a01:111:f403:2412::606; envelope-from=nicolinc@nvidia.com; helo=NAM10-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Jul 16, 2025 at 10:26:21AM +0000, Shameerali Kolothum Thodi wrote: > > On Mon, Jul 14, 2025 at 04:59:40PM +0100, Shameer Kolothum wrote: > > My vSMMU didn't work until I added entries like SIDSIZE, SSIDSIZE, > > TERM_MODEL, STALL_MODEL, and RIL. > > How come your vSMMU not working? Or you meant the assigned > dev is not working? The "dev" (behind the vSMMU) running in the guest I mean. > The emulation supports SIDSIZE = 16 and RIL. Could you please > share the difference between these values w.r.t host SMMUv3. My hardware doesn't support RIL while the VMM sets RIL. There are other conflicts like STALL_MODEL that affected the final two-stage STE in the host too. > Probably we should take a look at Intel vtd implementation mentioned > by Zhenzhong in the other thread where it looks like there seems to be > a property for each capability they care about. > > Probably something like, > -device arm-smmuv3,accel=on,pasid_cap=on, > > And then enabling all features related to pasid and on later when > we retrieve the HW_INFO on device plug, compare and fail if not? > > But I think on ARM, we still we have limitations in knowing the actual > host supported features through IDR. In that case, we can only assume > that user is making an informed decision while enabling these features. Yes, I think you are right about this approach. Maybe a "subversion" parameter could mask away quite a few bits like RIL BBML. But the tricky thing is that user might want a customization to those individual bits, because it has to match with the HW values to use the device correctly. Thanks Nicolin