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[213.67.3.247]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55f35c1222esm1136208e87.49.2025.08.24.09.09.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Aug 2025 09:09:12 -0700 (PDT) Date: Sun, 24 Aug 2025 18:09:12 +0200 From: "Edgar E. Iglesias" To: Corvin =?iso-8859-1?Q?K=F6hne?= Cc: qemu-devel@nongnu.org, Peter Maydell , Corvin =?iso-8859-1?Q?K=F6hne?= , qemu-arm@nongnu.org, Kevin Wolf , Paolo Bonzini , Alistair Francis , Yannick =?iso-8859-1?Q?Vo=DFen?= , Hanna Reitz , qemu-block@nongnu.org Subject: Re: [PATCH v2 05/14] hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in user mode Message-ID: References: <20250815090113.141641-1-corvin.koehne@gmail.com> <20250815090113.141641-6-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250815090113.141641-6-corvin.koehne@gmail.com> User-Agent: Mutt/2.2.14+84 (2efcabc4) (2025-03-23) Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Aug 15, 2025 at 11:01:03AM +0200, Corvin Köhne wrote: > From: YannickV > > All register bits are clear on write by writing 1s to those bits, however > the register bits will only be cleared if the condition that sets the > interrupt flag is no longer true. Since we can assume that programming > is always done, the `PCFG_DONE` flag is always set to 1, so it will not > never be cleared. > > Signed-off-by: Yannick Voßen > --- > hw/dma/xlnx-zynq-devcfg.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c > index f28d0015e6..60ea351494 100644 > --- a/hw/dma/xlnx-zynq-devcfg.c > +++ b/hw/dma/xlnx-zynq-devcfg.c > @@ -188,6 +188,8 @@ static void r_ixr_post_write(RegisterInfo *reg, uint64_t val) > { > XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque); > > + s->regs[R_INT_STS] |= R_INT_STS_PCFG_DONE_MASK; > + Looks like you've got some stray spaces in the empty line. I'm fine with this but another way to handle PCFG_DONE could be to have some state that goes true after the first programming. e.g: s->regs[R_INT_STS] |= s->pcfg_done ? R_INT_STS_PCFG_DONE_MASK : 0; On the other hand, for direct Linux boots we may want this to be always one... Anyway, with the whitespace fixes: Reviewed-by: Edgar E. Iglesias > xlnx_zynq_devcfg_update_ixr(s); > } > > -- > 2.50.1 >