From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: "Corvin Köhne" <corvin.koehne@gmail.com>
Cc: qemu-devel@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
"Corvin Köhne" <c.koehne@beckhoff.com>,
qemu-arm@nongnu.org, "Kevin Wolf" <kwolf@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Alistair Francis" <alistair@alistair23.me>,
"Yannick Voßen" <y.vossen@beckhoff.com>,
"Hanna Reitz" <hreitz@redhat.com>,
qemu-block@nongnu.org
Subject: Re: [PATCH v2 07/14] hw/dma/zynq-devcfg: Indicate power-up status of PL
Date: Sun, 24 Aug 2025 18:11:16 +0200 [thread overview]
Message-ID: <aKs5pO1qJ-h6MGIF@zapote> (raw)
In-Reply-To: <20250815090113.141641-8-corvin.koehne@gmail.com>
On Fri, Aug 15, 2025 at 11:01:05AM +0200, Corvin Köhne wrote:
> From: YannickV <Y.Vossen@beckhoff.com>
>
> It is assumed, that the programmable logic (PL) is always powered
> during emulation. Therefor the PCFG_POR_B bit in the MCTRL register
> is set.
>
> Signed-off-by: Yannick Voßen <y.vossen@beckhoff.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
> ---
> hw/dma/xlnx-zynq-devcfg.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c
> index c699df6ad4..064955a0f8 100644
> --- a/hw/dma/xlnx-zynq-devcfg.c
> +++ b/hw/dma/xlnx-zynq-devcfg.c
> @@ -333,7 +333,8 @@ static const RegisterAccessInfo xlnx_zynq_devcfg_regs_info[] = {
> /* Silicon 3.0 for version field, the mysterious reserved bit 23
> * and QEMU platform identifier.
> */
> - .reset = 0x2 << R_MCTRL_PS_VERSION_SHIFT | 1 << 23 | R_MCTRL_QEMU_MASK,
> + .reset = 0x2 << R_MCTRL_PS_VERSION_SHIFT | 1 << 23 |
> + R_MCTRL_PCFG_POR_B_MASK | R_MCTRL_QEMU_MASK,
> .ro = ~R_MCTRL_INT_PCAP_LPBK_MASK,
> .rsvd = 0x00f00303,
> },
> --
> 2.50.1
>
next prev parent reply other threads:[~2025-08-24 16:12 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-15 9:00 [PATCH v2 00/14] hw/arm: add Beckhoff CX7200 board Corvin Köhne
2025-08-15 9:00 ` [PATCH v2 01/14] hw/timer: Make frequency configurable Corvin Köhne
2025-08-19 16:37 ` Peter Maydell
2025-08-19 16:41 ` Peter Maydell
2025-08-15 9:01 ` [PATCH v2 02/14] hw/timer: Make PERIPHCLK period configurable Corvin Köhne
2025-08-19 16:38 ` Peter Maydell
2025-08-15 9:01 ` [PATCH v2 03/14] hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff Corvin Köhne
2025-08-15 9:01 ` [PATCH v2 04/14] hw/arm/zynq-devcfg: Prevent unintended unlock during initialization Corvin Köhne
2025-08-24 15:47 ` Edgar E. Iglesias
2025-08-15 9:01 ` [PATCH v2 05/14] hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in user mode Corvin Köhne
2025-08-24 16:09 ` Edgar E. Iglesias
2025-08-15 9:01 ` [PATCH v2 06/14] hw/dma/zynq-devcfg: Simulate dummy PL reset Corvin Köhne
2025-08-24 15:53 ` Edgar E. Iglesias
2025-08-15 9:01 ` [PATCH v2 07/14] hw/dma/zynq-devcfg: Indicate power-up status of PL Corvin Köhne
2025-08-24 16:11 ` Edgar E. Iglesias [this message]
2025-08-15 9:01 ` [PATCH v2 08/14] hw/dma/zynq-devcfg: Fix register memory Corvin Köhne
2025-08-15 9:01 ` [PATCH v2 09/14] hw/misc: Add dummy ZYNQ DDR controller Corvin Köhne
2025-08-19 15:43 ` Peter Maydell
2025-08-24 16:24 ` Edgar E. Iglesias
2025-08-15 9:01 ` [PATCH v2 10/14] hw/misc/zynq_slcr: Add logic for DCI configuration Corvin Köhne
2025-08-24 16:41 ` Edgar E. Iglesias
2025-08-15 9:01 ` [PATCH v2 11/14] hw/misc: Add Beckhoff CCAT device Corvin Köhne
2025-08-19 16:03 ` Peter Maydell
2025-10-15 9:22 ` Corvin Köhne
2025-08-15 9:01 ` [PATCH v2 12/14] hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d Corvin Köhne
2025-08-15 9:01 ` [PATCH v2 13/14] hw/arm: Add new machine based on xilinx-zynq-a9 for Beckhoff CX7200 Corvin Köhne
2025-08-15 9:01 ` [PATCH v2 14/14] docs/system/arm: Add support " Corvin Köhne
2025-08-15 18:06 ` [PATCH v2 00/14] hw/arm: add Beckhoff CX7200 board Peter Maydell
2025-08-19 16:40 ` Peter Maydell
2025-08-24 16:51 ` Edgar E. Iglesias
2025-10-15 9:26 ` Corvin Köhne
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