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[213.67.3.247]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55f35c8bceesm1151261e87.72.2025.08.24.09.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Aug 2025 09:41:57 -0700 (PDT) Date: Sun, 24 Aug 2025 18:41:56 +0200 From: "Edgar E. Iglesias" To: Corvin =?iso-8859-1?Q?K=F6hne?= Cc: qemu-devel@nongnu.org, Peter Maydell , Corvin =?iso-8859-1?Q?K=F6hne?= , qemu-arm@nongnu.org, Kevin Wolf , Paolo Bonzini , Alistair Francis , Yannick =?iso-8859-1?Q?Vo=DFen?= , Hanna Reitz , qemu-block@nongnu.org, "Edgar E. Iglesias" Subject: Re: [PATCH v2 10/14] hw/misc/zynq_slcr: Add logic for DCI configuration Message-ID: References: <20250815090113.141641-1-corvin.koehne@gmail.com> <20250815090113.141641-11-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250815090113.141641-11-corvin.koehne@gmail.com> User-Agent: Mutt/2.2.14+84 (2efcabc4) (2025-03-23) Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Aug 15, 2025 at 11:01:08AM +0200, Corvin Köhne wrote: > From: YannickV > > The registers for the digitally controlled impedance (DCI) clock are > part of the system level control registers (SLCR). The DONE bit in > the status register indicates a successfull DCI calibration. An > description of the calibration process can be found here: > https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/DDR-IOB-Impedance-Calibration > > The DCI control register and status register have been added. As soon > as the ENABLE and RESET bit are set, the RESET bit has also been toggled > to 0 before and the UPDATE_CONTROL is not set, the DONE bit in the status > register is set. If these bits change the DONE bit is reset. Note that the > option bits are not taken into consideration. > > Signed-off-by: Yannick Voßen > Reviewed-by: Edgar E. Iglesias BTW, I just noticed that this patch has style problems: e8874ea66c (HEAD, beckhoff) hw/misc/zynq_slcr: Add logic for DCI configuration ERROR: trailing whitespace #72: FILE: hw/misc/zynq_slcr.c:571: + if (!FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && $ total: 1 errors, 0 warnings, 61 lines checked > --- > hw/misc/zynq_slcr.c | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c > index a766bab182..8d15f0cc66 100644 > --- a/hw/misc/zynq_slcr.c > +++ b/hw/misc/zynq_slcr.c > @@ -180,6 +180,12 @@ REG32(GPIOB_CFG_HSTL, 0xb14) > REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18) > > REG32(DDRIOB, 0xb40) > +REG32(DDRIOB_DCI_CTRL, 0xb70) > + FIELD(DDRIOB_DCI_CTRL, RESET, 0, 1) > + FIELD(DDRIOB_DCI_CTRL, ENABLE, 1, 1) > + FIELD(DDRIOB_DCI_CTRL, UPDATE_CONTROL, 20, 1) > +REG32(DDRIOB_DCI_STATUS, 0xb74) > + FIELD(DDRIOB_DCI_STATUS, DONE, 13, 1) > #define DDRIOB_LENGTH 14 > > #define ZYNQ_SLCR_MMIO_SIZE 0x1000 > @@ -193,6 +199,8 @@ struct ZynqSLCRState { > > MemoryRegion iomem; > > + bool ddriob_dci_ctrl_reset_toggled; > + > uint32_t regs[ZYNQ_SLCR_NUM_REGS]; > > Clock *ps_clk; > @@ -331,6 +339,8 @@ static void zynq_slcr_reset_init(Object *obj, ResetType type) > > DB_PRINT("RESET\n"); > > + s->ddriob_dci_ctrl_reset_toggled = false; > + > s->regs[R_LOCKSTA] = 1; > /* 0x100 - 0x11C */ > s->regs[R_ARM_PLL_CTRL] = 0x0001A008; > @@ -418,6 +428,8 @@ static void zynq_slcr_reset_init(Object *obj, ResetType type) > s->regs[R_DDRIOB + 4] = s->regs[R_DDRIOB + 5] = s->regs[R_DDRIOB + 6] > = 0x00000e00; > s->regs[R_DDRIOB + 12] = 0x00000021; > + > + s->regs[R_DDRIOB_DCI_CTRL] = 0x00000020; > } > > static void zynq_slcr_reset_hold(Object *obj, ResetType type) > @@ -554,6 +566,25 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, > (int)offset, (unsigned)val & 0xFFFF); > } > return; > + > + case R_DDRIOB_DCI_CTRL: > + if (!FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && > + FIELD_EX32(s->regs[R_DDRIOB_DCI_CTRL], DDRIOB_DCI_CTRL, RESET)) { > + > + s->ddriob_dci_ctrl_reset_toggled = true; > + DB_PRINT("DDRIOB DCI CTRL RESET was toggled\n"); > + } > + > + if (FIELD_EX32(val, DDRIOB_DCI_CTRL, ENABLE) && > + FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && > + !FIELD_EX32(val, DDRIOB_DCI_CTRL, UPDATE_CONTROL) && > + s->ddriob_dci_ctrl_reset_toggled) { > + > + s->regs[R_DDRIOB_DCI_STATUS] |= R_DDRIOB_DCI_STATUS_DONE_MASK; > + } else { > + s->regs[R_DDRIOB_DCI_STATUS] &= ~R_DDRIOB_DCI_STATUS_DONE_MASK; > + } > + break; > } > > if (s->regs[R_LOCKSTA]) { > -- > 2.50.1 >