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From: "Daniel P. Berrangé" <berrange@redhat.com>
To: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
	"cfu@mips.com" <cfu@mips.com>, "mst@redhat.com" <mst@redhat.com>,
	"marcel.apfelbaum@gmail.com" <marcel.apfelbaum@gmail.com>,
	"dbarboza@ventanamicro.com" <dbarboza@ventanamicro.com>,
	"philmd@linaro.org" <philmd@linaro.org>
Subject: Re: [PATCH v7 08/14] hw/misc: Add RISC-V CMGCR device implementation
Date: Mon, 1 Sep 2025 11:48:12 +0100	[thread overview]
Message-ID: <aLV57BIImTTLbhbL@redhat.com> (raw)
In-Reply-To: <20250901102850.1172983-9-djordje.todorovic@htecgroup.com>

On Mon, Sep 01, 2025 at 10:29:04AM +0000, Djordje Todorovic wrote:
> Add RISC-V implementation of the Coherent Manager Global Control
> Register (CMGCR) device. It is based on the existing MIPS CMGCR
> implementation but adapted for RISC-V systems.
> 
> The CMGCR device provides global system control for multi-core
> configurations in RISC-V systems.
> 
> This is needed for the MIPS BOSTON AIA board.
> 
> Signed-off-by: Chao-ying Fu <cfu@mips.com>
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>  hw/misc/Kconfig               |   9 ++
>  hw/misc/meson.build           |   2 +
>  hw/misc/riscv_cmgcr.c         | 244 ++++++++++++++++++++++++++++++++++
>  include/hw/misc/riscv_cmgcr.h |  50 +++++++
>  4 files changed, 305 insertions(+)
>  create mode 100644 hw/misc/riscv_cmgcr.c
>  create mode 100644 include/hw/misc/riscv_cmgcr.h

> diff --git a/hw/misc/riscv_cmgcr.c b/hw/misc/riscv_cmgcr.c
> new file mode 100644
> index 0000000000..1093eede19
> --- /dev/null
> +++ b/hw/misc/riscv_cmgcr.c
> @@ -0,0 +1,244 @@
> +/*
> + * This file is subject to the terms and conditions of the GNU General Public
> + * License.  See the file "COPYING" in the main directory of this archive
> + * for more details.
> + *
> + * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
> + * Authors: Sanjay Lal <sanjayl@kymasys.com>
> + *
> + * Copyright (C) 2015 Imagination Technologies
> + *
> + * Copyright (C) 2025 MIPS
> + *
> + * SPDX-License-Identifier: LGPL-2.1-or-later

IIUC, you copied this from hw/misc/mips_cmgcr.c, which was
GPL-2.0-or-later and so you can't claim this is LGPL-2.1-or-later.

Since the orignial file didn't have a SPDX tag, don't add one
to this new file - leave the original GPL copyright header
untouched.

> diff --git a/include/hw/misc/riscv_cmgcr.h b/include/hw/misc/riscv_cmgcr.h
> new file mode 100644
> index 0000000000..d7145a51af
> --- /dev/null
> +++ b/include/hw/misc/riscv_cmgcr.h
> @@ -0,0 +1,50 @@
> +/*
> + * This file is subject to the terms and conditions of the GNU General Public
> + * License.  See the file "COPYING" in the main directory of this archive
> + * for more details.
> + *
> + * Copyright (C) 2015 Imagination Technologies
> + *
> + * Copyright (C) 2025 MIPS
> + *
> + * SPDX-License-Identifier: LGPL-2.1-or-later

Same point again


With regards,
Daniel
-- 
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  reply	other threads:[~2025-09-01 10:49 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-01 10:29 [PATCH v7 00/14] riscv: Add support for MIPS P8700 CPU Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 01/14] hw/intc: Allow gaps in hartids for aclint and aplic Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 02/14] target/riscv: Add cpu_set_exception_base Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 04/14] target/riscv: Add MIPS P8700 CSRs Djordje Todorovic
2025-09-01 10:41   ` Daniel P. Berrangé
2025-09-03  8:38     ` Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 03/14] target/riscv: Add MIPS P8700 CPU Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 05/14] target/riscv: Add mips.ccmov instruction Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 06/14] target/riscv: Add mips.pref instruction Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 08/14] hw/misc: Add RISC-V CMGCR device implementation Djordje Todorovic
2025-09-01 10:48   ` Daniel P. Berrangé [this message]
2025-09-01 10:29 ` [PATCH v7 07/14] target/riscv: Add Xmipslsp instructions Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 09/14] hw/misc: Add RISC-V CPC device implementation Djordje Todorovic
2025-09-01 10:49   ` Daniel P. Berrangé
2025-09-01 10:29 ` [PATCH v7 10/14] hw/riscv: Add support for RISCV CPS Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 11/14] hw/riscv: Add support for MIPS Boston-aia board mode Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 12/14] hw/pci: Allow explicit function numbers in pci Djordje Todorovic
2025-09-01 11:16   ` Philippe Mathieu-Daudé
2025-09-01 10:29 ` [PATCH v7 13/14] riscv/boston-aia: Add an e1000e NIC in slot 0 func 1 Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 14/14] test/functional: Add test for boston-aia board Djordje Todorovic

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