From: "Daniel P. Berrangé" <berrange@redhat.com>
To: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
"cfu@mips.com" <cfu@mips.com>, "mst@redhat.com" <mst@redhat.com>,
"marcel.apfelbaum@gmail.com" <marcel.apfelbaum@gmail.com>,
"dbarboza@ventanamicro.com" <dbarboza@ventanamicro.com>,
"philmd@linaro.org" <philmd@linaro.org>
Subject: Re: [PATCH v7 09/14] hw/misc: Add RISC-V CPC device implementation
Date: Mon, 1 Sep 2025 11:49:42 +0100 [thread overview]
Message-ID: <aLV6RjGTizwAbyd-@redhat.com> (raw)
In-Reply-To: <20250901102850.1172983-10-djordje.todorovic@htecgroup.com>
On Mon, Sep 01, 2025 at 10:29:05AM +0000, Djordje Todorovic wrote:
> Add RISC-V implementation of the Cluster Power Controller (CPC) device.
> It is based on the existing MIPS CPC implementations but adapted for
> RISC-V systems.
>
> The CPC device manages power control for CPU clusters in RISC-V
> systems.
>
> This is needed for the MIPS BOSTON AIA board.
>
> Signed-off-by: Chao-ying Fu <cfu@mips.com>
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> hw/misc/Kconfig | 4 +
> hw/misc/meson.build | 1 +
> hw/misc/riscv_cpc.c | 271 ++++++++++++++++++++++++++++++++++++
> include/hw/misc/riscv_cpc.h | 75 ++++++++++
> 4 files changed, 351 insertions(+)
> create mode 100644 hw/misc/riscv_cpc.c
> create mode 100644 include/hw/misc/riscv_cpc.h
>
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index c72927c3ff..1e35bcd443 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -124,11 +124,15 @@ config MIPS_ITU
> config RISCV_CMGCR
> bool
>
> +config RISCV_CPC
> + bool
> +
> config MIPS_BOSTON_AIA
> bool
> default y
> depends on RISCV64
> select RISCV_CMGCR
> + select RISCV_CPC
>
> config MPS2_FPGAIO
> bool
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index ef891e465b..1f9945755f 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -158,6 +158,7 @@ specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_cmgcr.c', 'mips_cp
> specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c'))
>
> specific_ss.add(when: 'CONFIG_RISCV_CMGCR', if_true: files('riscv_cmgcr.c'))
> +specific_ss.add(when: 'CONFIG_RISCV_CPC', if_true: files('riscv_cpc.c'))
>
> system_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c'))
>
> diff --git a/hw/misc/riscv_cpc.c b/hw/misc/riscv_cpc.c
> new file mode 100644
> index 0000000000..6a6cf72d45
> --- /dev/null
> +++ b/hw/misc/riscv_cpc.c
> @@ -0,0 +1,271 @@
> +/*
> + * Cluster Power Controller emulation
> + *
> + * Copyright (c) 2016 Imagination Technologies
> + *
> + * Copyright (c) 2025 MIPS
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + *
> + * SPDX-License-Identifier: LGPL-2.1-or-later
As this was copied from an existing file, just leave the original GPL
header here unchanged, don't add a SPDX tag to pre-existing code, only
to newly authored files.
> diff --git a/include/hw/misc/riscv_cpc.h b/include/hw/misc/riscv_cpc.h
> new file mode 100644
> index 0000000000..3e908f4f44
> --- /dev/null
> +++ b/include/hw/misc/riscv_cpc.h
> @@ -0,0 +1,75 @@
> +/*
> + * Cluster Power Controller emulation
> + *
> + * Copyright (c) 2016 Imagination Technologies
> + *
> + * Copyright (c) 2025 MIPS
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + *
> + * SPDX-License-Identifier: LGPL-2.1-or-later
> + *
> + */
Same points as above.
With regards,
Daniel
--
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next prev parent reply other threads:[~2025-09-01 10:50 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-01 10:29 [PATCH v7 00/14] riscv: Add support for MIPS P8700 CPU Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 02/14] target/riscv: Add cpu_set_exception_base Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 01/14] hw/intc: Allow gaps in hartids for aclint and aplic Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 04/14] target/riscv: Add MIPS P8700 CSRs Djordje Todorovic
2025-09-01 10:41 ` Daniel P. Berrangé
2025-09-03 8:38 ` Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 03/14] target/riscv: Add MIPS P8700 CPU Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 06/14] target/riscv: Add mips.pref instruction Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 05/14] target/riscv: Add mips.ccmov instruction Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 08/14] hw/misc: Add RISC-V CMGCR device implementation Djordje Todorovic
2025-09-01 10:48 ` Daniel P. Berrangé
2025-09-01 10:29 ` [PATCH v7 07/14] target/riscv: Add Xmipslsp instructions Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 09/14] hw/misc: Add RISC-V CPC device implementation Djordje Todorovic
2025-09-01 10:49 ` Daniel P. Berrangé [this message]
2025-09-01 10:29 ` [PATCH v7 10/14] hw/riscv: Add support for RISCV CPS Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 11/14] hw/riscv: Add support for MIPS Boston-aia board mode Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 12/14] hw/pci: Allow explicit function numbers in pci Djordje Todorovic
2025-09-01 11:16 ` Philippe Mathieu-Daudé
2025-09-01 10:29 ` [PATCH v7 13/14] riscv/boston-aia: Add an e1000e NIC in slot 0 func 1 Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 14/14] test/functional: Add test for boston-aia board Djordje Todorovic
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