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Mon, 1 Sep 2025 10:49:49 +0000 (UTC) Received: from redhat.com (unknown [10.42.28.100]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 8ACA7180028F; Mon, 1 Sep 2025 10:49:46 +0000 (UTC) Date: Mon, 1 Sep 2025 11:49:42 +0100 From: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= To: Djordje Todorovic Cc: "qemu-devel@nongnu.org" , "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" , "philmd@linaro.org" Subject: Re: [PATCH v7 09/14] hw/misc: Add RISC-V CPC device implementation Message-ID: References: <20250901102850.1172983-1-djordje.todorovic@htecgroup.com> <20250901102850.1172983-10-djordje.todorovic@htecgroup.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20250901102850.1172983-10-djordje.todorovic@htecgroup.com> User-Agent: Mutt/2.2.14 (2025-02-20) X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass client-ip=170.10.129.124; envelope-from=berrange@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Sep 01, 2025 at 10:29:05AM +0000, Djordje Todorovic wrote: > Add RISC-V implementation of the Cluster Power Controller (CPC) device. > It is based on the existing MIPS CPC implementations but adapted for > RISC-V systems. > > The CPC device manages power control for CPU clusters in RISC-V > systems. > > This is needed for the MIPS BOSTON AIA board. > > Signed-off-by: Chao-ying Fu > Signed-off-by: Djordje Todorovic > Reviewed-by: Daniel Henrique Barboza > --- > hw/misc/Kconfig | 4 + > hw/misc/meson.build | 1 + > hw/misc/riscv_cpc.c | 271 ++++++++++++++++++++++++++++++++++++ > include/hw/misc/riscv_cpc.h | 75 ++++++++++ > 4 files changed, 351 insertions(+) > create mode 100644 hw/misc/riscv_cpc.c > create mode 100644 include/hw/misc/riscv_cpc.h > > diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig > index c72927c3ff..1e35bcd443 100644 > --- a/hw/misc/Kconfig > +++ b/hw/misc/Kconfig > @@ -124,11 +124,15 @@ config MIPS_ITU > config RISCV_CMGCR > bool > > +config RISCV_CPC > + bool > + > config MIPS_BOSTON_AIA > bool > default y > depends on RISCV64 > select RISCV_CMGCR > + select RISCV_CPC > > config MPS2_FPGAIO > bool > diff --git a/hw/misc/meson.build b/hw/misc/meson.build > index ef891e465b..1f9945755f 100644 > --- a/hw/misc/meson.build > +++ b/hw/misc/meson.build > @@ -158,6 +158,7 @@ specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_cmgcr.c', 'mips_cp > specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c')) > > specific_ss.add(when: 'CONFIG_RISCV_CMGCR', if_true: files('riscv_cmgcr.c')) > +specific_ss.add(when: 'CONFIG_RISCV_CPC', if_true: files('riscv_cpc.c')) > > system_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c')) > > diff --git a/hw/misc/riscv_cpc.c b/hw/misc/riscv_cpc.c > new file mode 100644 > index 0000000000..6a6cf72d45 > --- /dev/null > +++ b/hw/misc/riscv_cpc.c > @@ -0,0 +1,271 @@ > +/* > + * Cluster Power Controller emulation > + * > + * Copyright (c) 2016 Imagination Technologies > + * > + * Copyright (c) 2025 MIPS > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + * > + * SPDX-License-Identifier: LGPL-2.1-or-later As this was copied from an existing file, just leave the original GPL header here unchanged, don't add a SPDX tag to pre-existing code, only to newly authored files. > diff --git a/include/hw/misc/riscv_cpc.h b/include/hw/misc/riscv_cpc.h > new file mode 100644 > index 0000000000..3e908f4f44 > --- /dev/null > +++ b/include/hw/misc/riscv_cpc.h > @@ -0,0 +1,75 @@ > +/* > + * Cluster Power Controller emulation > + * > + * Copyright (c) 2016 Imagination Technologies > + * > + * Copyright (c) 2025 MIPS > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + * > + * SPDX-License-Identifier: LGPL-2.1-or-later > + * > + */ Same points as above. With regards, Daniel -- |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o- https://fstop138.berrange.com :| |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|