Re: [PATCH v5 01/47] hw/arm/xlnx-versal: split the xlnx-versal type

["Edgar E. Iglesias" via <qemu-devel@nongnu.org>]

On Fri, Sep 12, 2025 at 12:00:10PM +0200, Luc Michel wrote:
> Split the xlnx-versal device into two classes, a base, abstract class
> and the existing concrete one. Introduce a VersalVersion type that will
> be used across several device models when versal2 implementation is
> added.
> 
> This is in preparation for versal2 implementation.
> 
> Signed-off-by: Luc Michel <luc.michel@amd.com>
> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>


> ---
>  include/hw/arm/xlnx-versal-version.h | 15 ++++++++++++++
>  include/hw/arm/xlnx-versal.h         | 12 ++++++++++-
>  hw/arm/xlnx-versal.c                 | 31 +++++++++++++++++++++-------
>  3 files changed, 50 insertions(+), 8 deletions(-)
>  create mode 100644 include/hw/arm/xlnx-versal-version.h
> 
> diff --git a/include/hw/arm/xlnx-versal-version.h b/include/hw/arm/xlnx-versal-version.h
> new file mode 100644
> index 00000000000..c4307d1304a
> --- /dev/null
> +++ b/include/hw/arm/xlnx-versal-version.h
> @@ -0,0 +1,15 @@
> +/*
> + * AMD Versal versions
> + *
> + * Copyright (c) 2025 Advanced Micro Devices, Inc.
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#ifndef HW_ARM_XLNX_VERSAL_VERSION_H
> +#define HW_ARM_XLNX_VERSAL_VERSION_H
> +
> +typedef enum VersalVersion {
> +    VERSAL_VER_VERSAL,
> +} VersalVersion;
> +
> +#endif
> diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
> index 05ed641b6b6..1f92e314d6c 100644
> --- a/include/hw/arm/xlnx-versal.h
> +++ b/include/hw/arm/xlnx-versal.h
> @@ -1,9 +1,10 @@
>  /*
>   * Model of the Xilinx Versal
>   *
>   * Copyright (c) 2018 Xilinx Inc.
> + * Copyright (c) 2025 Advanced Micro Devices, Inc.
>   * Written by Edgar E. Iglesias
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 or
>   * (at your option) any later version.
> @@ -33,13 +34,16 @@
>  #include "hw/misc/xlnx-versal-trng.h"
>  #include "hw/net/xlnx-versal-canfd.h"
>  #include "hw/misc/xlnx-versal-cfu.h"
>  #include "hw/misc/xlnx-versal-cframe-reg.h"
>  #include "target/arm/cpu.h"
> +#include "hw/arm/xlnx-versal-version.h"
> +
> +#define TYPE_XLNX_VERSAL_BASE "xlnx-versal-base"
> +OBJECT_DECLARE_TYPE(Versal, VersalClass, XLNX_VERSAL_BASE)
>  
>  #define TYPE_XLNX_VERSAL "xlnx-versal"
> -OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
>  
>  #define XLNX_VERSAL_NR_ACPUS   2
>  #define XLNX_VERSAL_NR_RCPUS   2
>  #define XLNX_VERSAL_NR_UARTS   2
>  #define XLNX_VERSAL_NR_GEMS    2
> @@ -135,10 +139,16 @@ struct Versal {
>      struct {
>          MemoryRegion *mr_ddr;
>      } cfg;
>  };
>  
> +struct VersalClass {
> +    SysBusDeviceClass parent;
> +
> +    VersalVersion version;
> +};
> +
>  /* Memory-map and IRQ definitions. Copied a subset from
>   * auto-generated files.  */
>  
>  #define VERSAL_GIC_MAINT_IRQ        9
>  #define VERSAL_TIMER_VIRT_IRQ       11
> diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
> index a42b9e7140b..4da656318f6 100644
> --- a/hw/arm/xlnx-versal.c
> +++ b/hw/arm/xlnx-versal.c
> @@ -1,9 +1,10 @@
>  /*
>   * Xilinx Versal SoC model.
>   *
>   * Copyright (c) 2018 Xilinx Inc.
> + * Copyright (c) 2025 Advanced Micro Devices, Inc.
>   * Written by Edgar E. Iglesias
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 or
>   * (at your option) any later version.
> @@ -918,11 +919,11 @@ static void versal_unimp(Versal *s)
>                                  gpio_in);
>  }
>  
>  static void versal_realize(DeviceState *dev, Error **errp)
>  {
> -    Versal *s = XLNX_VERSAL(dev);
> +    Versal *s = XLNX_VERSAL_BASE(dev);
>      qemu_irq pic[XLNX_VERSAL_NR_IRQS];
>  
>      versal_create_apu_cpus(s);
>      versal_create_apu_gic(s, pic);
>      versal_create_rpu_cpus(s);
> @@ -953,13 +954,13 @@ static void versal_realize(DeviceState *dev, Error **errp)
>      memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
>      memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0,
>                                          &s->lpd.rpu.mr_ps_alias, 0);
>  }
>  
> -static void versal_init(Object *obj)
> +static void versal_base_init(Object *obj)
>  {
> -    Versal *s = XLNX_VERSAL(obj);
> +    Versal *s = XLNX_VERSAL_BASE(obj);
>  
>      memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
>      memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX);
>      memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
>      memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s),
> @@ -973,28 +974,44 @@ static const Property versal_properties[] = {
>                        TYPE_CAN_BUS, CanBusState *),
>      DEFINE_PROP_LINK("canbus1", Versal, lpd.iou.canbus[1],
>                        TYPE_CAN_BUS, CanBusState *),
>  };
>  
> -static void versal_class_init(ObjectClass *klass, const void *data)
> +static void versal_base_class_init(ObjectClass *klass, const void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(klass);
>  
>      dc->realize = versal_realize;
>      device_class_set_props(dc, versal_properties);
>      /* No VMSD since we haven't got any top-level SoC state to save.  */
>  }
>  
> -static const TypeInfo versal_info = {
> -    .name = TYPE_XLNX_VERSAL,
> +static void versal_class_init(ObjectClass *klass, const void *data)
> +{
> +    VersalClass *vc = XLNX_VERSAL_BASE_CLASS(klass);
> +
> +    vc->version = VERSAL_VER_VERSAL;
> +}
> +
> +static const TypeInfo versal_base_info = {
> +    .name = TYPE_XLNX_VERSAL_BASE,
>      .parent = TYPE_SYS_BUS_DEVICE,
>      .instance_size = sizeof(Versal),
> -    .instance_init = versal_init,
> +    .instance_init = versal_base_init,
> +    .class_init = versal_base_class_init,
> +    .class_size = sizeof(VersalClass),
> +    .abstract = true,
> +};
> +
> +static const TypeInfo versal_info = {
> +    .name = TYPE_XLNX_VERSAL,
> +    .parent = TYPE_XLNX_VERSAL_BASE,
>      .class_init = versal_class_init,
>  };
>  
>  static void versal_register_types(void)
>  {
> +    type_register_static(&versal_base_info);
>      type_register_static(&versal_info);
>  }
>  
>  type_init(versal_register_types);
> -- 
> 2.50.1
>