From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
To: Luc Michel <luc.michel@amd.com>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Peter Maydell" <peter.maydell@linaro.org>,
"Francisco Iglesias" <francisco.iglesias@amd.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Alistair Francis" <alistair@alistair23.me>,
"Frederic Konrad" <frederic.konrad@amd.com>,
"Sai Pavan Boddu" <sai.pavan.boddu@amd.com>
Subject: Re: [PATCH v5 02/47] hw/arm/xlnx-versal: prepare for FDT creation
Date: Thu, 18 Sep 2025 08:10:16 +0200 [thread overview]
Message-ID: <aMugpMt4qU4XSnay@zapote> (raw)
In-Reply-To: <aMkR9fr7ITfggWV7@XFR-LUMICHEL-L2.amd.com>
On Tue, Sep 16, 2025 at 09:30:46AM +0200, Luc Michel wrote:
> Hi Edgar,
>
> On 19:17 Fri 12 Sep , Edgar E. Iglesias wrote:
> > On Fri, Sep 12, 2025 at 12:00:11PM +0200, Luc Michel wrote:
> > > The following commits will move FDT creation logic from the
> > > xlnx-versal-virt machine to the xlnx-versal SoC itself. Prepare this by
> > > passing the FDT handle to the SoC before it is realized. If no FDT is
> > > passed, a dummy one is created internally as a stub to the fdt function
> > > calls.
> > >
> > > For now the SoC only creates the two clock nodes. The ones from the
> > > xlnx-versal virt machine are renamed with a `old-' prefix and will be
> > > removed once they are not referenced anymore.
> >
> >
> > Hi Luc,
> >
> >
> >
> > >
> > > Signed-off-by: Luc Michel <luc.michel@amd.com>
> > > Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
> > > ---
> > > include/hw/arm/xlnx-versal.h | 12 ++++++++++++
> > > hw/arm/xlnx-versal-virt.c | 9 ++++++---
> > > hw/arm/xlnx-versal.c | 28 ++++++++++++++++++++++++++++
> > > 3 files changed, 46 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
> > > index 1f92e314d6c..f2a62b43552 100644
> > > --- a/include/hw/arm/xlnx-versal.h
> > > +++ b/include/hw/arm/xlnx-versal.h
> > > @@ -134,21 +134,33 @@ struct Versal {
> > > XlnxVersalCFrameBcastReg cframe_bcast;
> > >
> > > OrIRQState apb_irq_orgate;
> > > } pmc;
> > >
> > > + struct {
> > > + uint32_t clk_25mhz;
> > > + uint32_t clk_125mhz;
> > > + } phandle;
> > > +
> > > struct {
> > > MemoryRegion *mr_ddr;
> > > + void *fdt;
> > > } cfg;
> > > };
> > >
> > > struct VersalClass {
> > > SysBusDeviceClass parent;
> > >
> > > VersalVersion version;
> > > };
> > >
> > > +static inline void versal_set_fdt(Versal *s, void *fdt)
> > > +{
> > > + g_assert(!qdev_is_realized(DEVICE(s)));
> > > + s->cfg.fdt = fdt;
> > > +}
> > > +
> >
> > Should this be a property of some sort? it looks a little odd to bypass QOM..
>
> fdt being a void* and not an Object*, it's not directly possible AFAIK.
> I don't see it being an issue here because the Versal SoC code is
> tightly coupled to the versal-virt machine code (the machine is
> basically the sole user of the SoC). Even if it was not the case, the
> SoC interface is fully specified in xlnx-versal.h and any user can
> leverage it just fine. I guess QOM/qdev abstractions are necessary when
> we don't include the .h and only rely on the type name (QMP, HPM
> use-cases, ...).
Yes, and for example the dynamic machine creation that Mirela
prototyped. I don't feel very strongly about this and I'm fine either
way. We can change things if a dynamic machine implementation comes
along.
>
> [snip]
>
> > > +
> > > static void versal_realize(DeviceState *dev, Error **errp)
> > > {
> > > Versal *s = XLNX_VERSAL_BASE(dev);
> > > qemu_irq pic[XLNX_VERSAL_NR_IRQS];
> > >
> > > + if (s->cfg.fdt == NULL) {
> > > + int fdt_size;
> > > +
> > > + s->cfg.fdt = create_device_tree(&fdt_size);
> > > + }
> > > +
> > > + s->phandle.clk_25mhz = fdt_add_clk_node(s, "/clk25", 25 * 1000 * 1000);
> > > + s->phandle.clk_125mhz = fdt_add_clk_node(s, "/clk125", 125 * 1000 * 1000);
> > > +
> >
> > Should we be adding nodes if s->cfg.fdt wasn't created by us?
> > If the user passes a dtb, I wonder if we should just assume the user
> > knows what they are doing and use it as is...
> >
> > Or do you have use-cases where it makes sense?
>
> Note that the device tree created in the SoC code is just a dummy one to
> avoid crashing when the SoC user does not provide one, as stated in the
> commit message:
>
> "If no FDT is passed, a dummy one is created internally as a stub to the
> fdt function calls."
Aha, thanks!
But then is there really a case when the dummy one is needed? won't
versal-virt always pass an fdt?
If that is the case then maybe we could just assert(s->cfg.fdt);
>
> This code path should not be reached in normal versal-virt machine
> use-case. We rely on the one given by the machine code through the
> versal_set_fdt function.
>
> Then to answer the question about the user providing a DTB, I stick to
> the existing behaviour before the refactoring. s->binfo.get_dtb is still
> set in the machine code and provided to the ARM virtual bootloader. The
> bootloader uses it only if no DTB is provided by the user.
Got it, thanks!
>
> Thanks
>
> --
> Luc
next prev parent reply other threads:[~2025-09-18 6:10 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-12 10:00 [PATCH v5 00/47] AMD Versal Gen 2 support Luc Michel
2025-09-12 10:00 ` [PATCH v5 01/47] hw/arm/xlnx-versal: split the xlnx-versal type Luc Michel
2025-09-12 17:07 ` Edgar E. Iglesias via
2025-09-12 10:00 ` [PATCH v5 02/47] hw/arm/xlnx-versal: prepare for FDT creation Luc Michel
2025-09-12 17:17 ` Edgar E. Iglesias
2025-09-16 7:30 ` Luc Michel
2025-09-18 6:10 ` Edgar E. Iglesias [this message]
2025-09-25 18:45 ` Edgar E. Iglesias
2025-09-26 6:32 ` Luc Michel
2025-09-12 10:00 ` [PATCH v5 03/47] hw/arm/xlnx-versal: uart: refactor creation Luc Michel
2025-09-12 17:22 ` Edgar E. Iglesias
2025-09-16 7:34 ` Luc Michel
2025-09-12 10:00 ` [PATCH v5 04/47] hw/arm/xlnx-versal: canfd: " Luc Michel
2025-09-12 17:31 ` Edgar E. Iglesias via
2025-09-16 7:38 ` Luc Michel
2025-09-12 10:00 ` [PATCH v5 05/47] hw/arm/xlnx-versal: sdhci: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 06/47] hw/arm/xlnx-versal: gem: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 07/47] hw/arm/xlnx-versal: adma: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 08/47] hw/arm/xlnx-versal: xram: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 09/47] hw/arm/xlnx-versal: usb: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 10/47] hw/arm/xlnx-versal: efuse: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 11/47] hw/arm/xlnx-versal: ospi: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 12/47] hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs Luc Michel
2025-09-12 10:00 ` [PATCH v5 13/47] hw/arm/xlnx-versal: PMC IOU SCLR: refactor creation Luc Michel
2025-09-12 10:00 ` [PATCH v5 14/47] hw/arm/xlnx-versal: bbram: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 15/47] hw/arm/xlnx-versal: trng: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 16/47] hw/arm/xlnx-versal: rtc: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 17/47] hw/arm/xlnx-versal: cfu: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 18/47] hw/arm/xlnx-versal: crl: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 19/47] hw/arm/xlnx-versal-virt: virtio: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 20/47] hw/arm/xlnx-versal: refactor CPU cluster creation Luc Michel
2025-09-12 10:00 ` [PATCH v5 21/47] hw/arm/xlnx-versal: add the mp_affinity property to the CPU mapping Luc Michel
2025-09-12 10:00 ` [PATCH v5 22/47] hw/arm/xlnx-versal: instantiate the GIC ITS in the APU Luc Michel
2025-09-12 10:00 ` [PATCH v5 23/47] hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property Luc Michel
2025-09-12 10:00 ` [PATCH v5 24/47] hw/arm/xlnx-versal: add support for multiple GICs Luc Michel
2025-09-12 10:00 ` [PATCH v5 25/47] hw/arm/xlnx-versal: add support for GICv2 Luc Michel
2025-09-12 10:00 ` [PATCH v5 26/47] hw/arm/xlnx-versal: rpu: refactor creation Luc Michel
2025-09-12 10:00 ` [PATCH v5 27/47] hw/arm/xlnx-versal: ocm: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 28/47] hw/arm/xlnx-versal: ddr: " Luc Michel
2025-09-12 10:00 ` [PATCH v5 29/47] hw/arm/xlnx-versal: add the versal_get_num_cpu accessor Luc Michel
2025-09-12 10:00 ` [PATCH v5 30/47] hw/misc/xlnx-versal-crl: remove unnecessary include directives Luc Michel
2025-09-12 10:00 ` [PATCH v5 31/47] hw/misc/xlnx-versal-crl: split into base/concrete classes Luc Michel
2025-09-12 10:00 ` [PATCH v5 32/47] hw/misc/xlnx-versal-crl: refactor device reset logic Luc Michel
2025-09-12 10:00 ` [PATCH v5 33/47] hw/arm/xlnx-versal: reconnect the CRL to the other devices Luc Michel
2025-09-12 10:00 ` [PATCH v5 34/47] hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices Luc Michel
2025-09-12 10:00 ` [PATCH v5 35/47] hw/arm/xlnx-versal: tidy up Luc Michel
2025-09-12 10:00 ` [PATCH v5 36/47] hw/misc/xlnx-versal-crl: add the versal2 version Luc Michel
2025-09-12 10:00 ` [PATCH v5 37/47] hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMap Luc Michel
2025-09-12 10:00 ` [PATCH v5 38/47] hw/arm/xlnx-versal: add the target field in IRQ descriptor Luc Michel
2025-09-12 10:00 ` [PATCH v5 39/47] target/arm/tcg/cpu64: add the cortex-a78ae CPU Luc Michel
2025-09-16 14:31 ` Peter Maydell
2025-09-12 10:00 ` [PATCH v5 40/47] hw/arm/xlnx-versal: add versal2 SoC Luc Michel
2025-09-12 10:00 ` [PATCH v5 41/47] hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt Luc Michel
2025-09-12 10:00 ` [PATCH v5 42/47] hw/arm/xlnx-versal-virt: split into base/concrete classes Luc Michel
2025-09-12 10:00 ` [PATCH v5 43/47] hw/arm/xlnx-versal-virt: tidy up Luc Michel
2025-09-12 10:00 ` [PATCH v5 44/47] docs/system/arm/xlnx-versal-virt: update supported devices Luc Michel
2025-09-12 10:00 ` [PATCH v5 45/47] docs/system/arm/xlnx-versal-virt: add a note about dumpdtb Luc Michel
2025-09-12 10:00 ` [PATCH v5 46/47] hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine Luc Michel
2025-09-12 10:00 ` [PATCH v5 47/47] tests/functional/test_aarch64_xlnx_versal: test the versal2 machine Luc Michel
2025-09-25 15:41 ` [PATCH v5 00/47] AMD Versal Gen 2 support Peter Maydell
2025-09-25 18:38 ` Edgar E. Iglesias
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