From: Zhao Liu <zhao1.liu@intel.com>
To: Ewan Hai <ewanhai-oc@zhaoxin.com>
Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, ewanhai@zhaoxin.com,
cobechen@zhaoxin.com
Subject: Re: [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server CPU model
Date: Mon, 27 Oct 2025 14:14:16 +0800 [thread overview]
Message-ID: <aP8NuLzItpNzt6DJ@intel.com> (raw)
In-Reply-To: <53c9af0b-49e2-4ec3-8846-01d44b2a9745@zhaoxin.com>
> >> In QEMU, vCPU models default to '.version = 1'. Since there is currently
> >> no '.features[index]' mapping for the "x-force-cpuid-0x1f" property, this
> >> patch adds that property to the v1 version of the model.
> >
> > I'm preparing the CPU model for Diamond Rapids, and also meet this
> > issue.
> >
> > Well, I happen to have a patch for this and I think you could give it
> > a try. :)
>
> That's good news. I'll test your patch and update mine accordingly.
> When I send out v2, should I note in the cover letter that my patches are based
> on your "0x1f option" patch?
Please feel free to pick that patch into your series.
Regards,
Zhao
next prev parent reply other threads:[~2025-10-27 5:52 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-23 2:11 [PATCH 0/3] target/i386: Add support for Zhaoxin Shijidadao vCPU models Ewan Hai
2025-09-23 2:11 ` [PATCH 1/3] target/i386: Add cache model for Zhaoxin Shijidadao vCPUs Ewan Hai
2025-09-23 2:11 ` [PATCH 2/3] target/i386: Introduce Zhaoxin Shijidadao-Client CPU model Ewan Hai
2025-09-23 2:11 ` [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server " Ewan Hai
2025-10-24 7:15 ` Zhao Liu
2025-10-27 3:42 ` Ewan Hai
2025-10-27 6:14 ` Zhao Liu [this message]
2025-10-24 7:18 ` [PATCH] i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f Zhao Liu
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