[PATCH 0/3] target/i386: Add support for Zhaoxin Shijidadao vCPU models

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* [PATCH 0/3] target/i386: Add support for Zhaoxin Shijidadao vCPU models
@ 2025-09-23  2:11 Ewan Hai
  2025-09-23  2:11 ` [PATCH 1/3] target/i386: Add cache model for Zhaoxin Shijidadao vCPUs Ewan Hai
                   ` (2 more replies)
  0 siblings, 3 replies; 8+ messages in thread
From: Ewan Hai @ 2025-09-23  2:11 UTC (permalink / raw)
  To: pbonzini, zhao1.liu; +Cc: qemu-devel

This patchset introduces cache enumeration and two vCPU models (Client
and Server) for the Zhaoxin "Shijidadao" architecture. With these
additions, QEMU can expose the core identity and features of this
architecture without relying on host-passthrough.

There are several points that may need particular attention from
maintainers:

1. The Shijidadao-Client model uses '.version = 1' to represent the
   hardware v1 revision, with 'version=2' added to capture v2
   differences. Please check whether this usage aligns with existing
   versioning practices.

2. For both Shijidadao-Client and Shijidadao-Server, the
   "x-force-cpuid-0x1f" feature is placed under the version 1
   definition. At present there is no mechanism to represent this
   feature via `.features[index]` in the default model definition,
   so attaching it to v1 is the only available option. Feedback on
   whether this placement is acceptable would be appreciated.

3. The Shijidadao-Server model enables the 'core-capability' bit by
   default, but KVM does not yet virtualize the corresponding MSR.
   Guidance on whether this setting should remain in the model is
   requested.

Thanks for your time reviewing this series!

Ewan Hai (3):
  target/i386: Add cache model for Zhaoxin Shijidadao vCPUs
  target/i386: Introduce Zhaoxin Shijidadao-Client CPU model
  target/i386: Introduce Zhaoxin Shijidadao-Server CPU model

 target/i386/cpu.c | 385 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 385 insertions(+)

-- 
2.34.1

^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH 1/3] target/i386: Add cache model for Zhaoxin Shijidadao vCPUs
  2025-09-23  2:11 [PATCH 0/3] target/i386: Add support for Zhaoxin Shijidadao vCPU models Ewan Hai
@ 2025-09-23  2:11 ` Ewan Hai
  2025-09-23  2:11 ` [PATCH 2/3] target/i386: Introduce Zhaoxin Shijidadao-Client CPU model Ewan Hai
  2025-09-23  2:11 ` [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server " Ewan Hai
  2 siblings, 0 replies; 8+ messages in thread
From: Ewan Hai @ 2025-09-23  2:11 UTC (permalink / raw)
  To: pbonzini, zhao1.liu; +Cc: qemu-devel

Zhaoxin "Shijidadao" vCPUs require built-in cache enumeration in QEMU
to properly report CPUID leaf 0x4 and 0x80000005/0x80000006 when
'host-cache-info' is disabled.

This patch defines the L1/L2/L3 cache parameters for the Shijidadao
architecture, preparing for use in both client and server models.

Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 target/i386/cpu.c | 99 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6d85149e6e..679f9d3970 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3262,6 +3262,105 @@ static const CPUCaches yongfeng_cache_info = {
     },
 };
 
+static const CPUCaches shijidadao_cache_info = {
+    .l1d_cache = &(CPUCacheInfo) {
+        /* CPUID 0x4.0x0.EAX */
+        .type = DATA_CACHE,
+        .level = 1,
+        .self_init = true,
+
+        /* CPUID 0x4.0x0.EBX */
+        .line_size = 64,
+        .partitions = 1,
+        .associativity = 8,
+
+        /* CPUID 0x4.0x0.ECX */
+        .sets = 64,
+
+        /* CPUID 0x4.0x0.EDX */
+        .no_invd_sharing = false,
+        .inclusive = false,
+        .complex_indexing = false,
+
+        /* CPUID 0x80000005.ECX */
+        .lines_per_tag = 1,
+        .size = 32 * KiB,
+
+        .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+    },
+    .l1i_cache = &(CPUCacheInfo) {
+        /* CPUID 0x4.0x1.EAX */
+        .type = INSTRUCTION_CACHE,
+        .level = 1,
+        .self_init = true,
+
+        /* CPUID 0x4.0x1.EBX */
+        .line_size = 64,
+        .partitions = 1,
+        .associativity = 16,
+
+        /* CPUID 0x4.0x1.ECX */
+        .sets = 64,
+
+        /* CPUID 0x4.0x1.EDX */
+        .no_invd_sharing = false,
+        .inclusive = false,
+        .complex_indexing = false,
+
+        /* CPUID 0x80000005.EDX */
+        .lines_per_tag = 1,
+        .size = 64 * KiB,
+
+        .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+    },
+    .l2_cache = &(CPUCacheInfo) {
+        /* CPUID 0x4.0x2.EAX */
+        .type = UNIFIED_CACHE,
+        .level = 2,
+        .self_init = true,
+
+        /* CPUID 0x4.0x2.EBX */
+        .line_size = 64,
+        .partitions = 1,
+        .associativity = 8,
+
+        /* CPUID 0x4.0x2.ECX */
+        .sets = 1024,
+
+        /* CPUID 0x4.0x2.EDX */
+        .no_invd_sharing = false,
+        .inclusive = true,
+        .complex_indexing = false,
+
+        /* CPUID 0x80000006.ECX */
+        .size = 512 * KiB,
+
+        .share_level = CPU_TOPOLOGY_LEVEL_CORE,
+    },
+    .l3_cache = &(CPUCacheInfo) {
+        /* CPUID 0x4.0x3.EAX */
+        .type = UNIFIED_CACHE,
+        .level = 3,
+        .self_init = true,
+
+        /* CPUID 0x4.0x3.EBX */
+        .line_size = 64,
+        .partitions = 1,
+        .associativity = 16,
+
+        /* CPUID 0x4.0x3.ECX */
+        .sets = 32768,
+
+        /* CPUID 0x4.0x3.EDX */
+        .no_invd_sharing = false,
+        .inclusive = true,
+        .complex_indexing = false,
+
+        .size = 32 * MiB,
+        .share_level = CPU_TOPOLOGY_LEVEL_DIE,
+    },
+};
+
 /* The following VMX features are not supported by KVM and are left out in the
  * CPU definitions:
  *
-- 
2.34.1



^ permalink raw reply related	[flat|nested] 8+ messages in thread

* [PATCH 2/3] target/i386: Introduce Zhaoxin Shijidadao-Client CPU model
  2025-09-23  2:11 [PATCH 0/3] target/i386: Add support for Zhaoxin Shijidadao vCPU models Ewan Hai
  2025-09-23  2:11 ` [PATCH 1/3] target/i386: Add cache model for Zhaoxin Shijidadao vCPUs Ewan Hai
@ 2025-09-23  2:11 ` Ewan Hai
  2025-09-23  2:11 ` [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server " Ewan Hai
  2 siblings, 0 replies; 8+ messages in thread
From: Ewan Hai @ 2025-09-23  2:11 UTC (permalink / raw)
  To: pbonzini, zhao1.liu; +Cc: qemu-devel

Zhaoxin "Shijidadao-Client" hardware has two revisions:

* v1 supports SMAP but lacks XSAVEC, XGETBV1, XSAVES, and VMX-XSAVES
* v2 provides XSAVEC/XGETBV1/XSAVES/VMX-XSAVES but does not support SMAP

Since QEMU CPU models default to '.version = 1', this patch keeps the same
definition for v1 and adds the "x-force-cpuid-0x1f" property, while
introducing 'version=2' to reflect the differences in v2. This allows both
hardware revisions to be covered by a single CPU model while preserving
the existing versioning logic.

Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 target/i386/cpu.c | 147 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 147 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 679f9d3970..d17284e300 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6747,6 +6747,153 @@ static const X86CPUDefinition builtin_x86_defs[] = {
         .model_id = "AMD EPYC-Turin Processor",
         .cache_info = &epyc_turin_cache_info,
     },
+    {
+        .name = "Shijidadao-Client",
+        .level = 0x1f,
+        .vendor = CPUID_VENDOR_ZHAOXIN1,
+        .family = 7,
+        .model = 0x6b,
+        .stepping = 1,
+        /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */
+        .features[FEAT_1_EDX] =
+            CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+            CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
+            CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
+            CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
+            CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87,
+        /*
+         * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2,
+         * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX
+         */
+        .features[FEAT_1_ECX] =
+            CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
+            CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER |
+            CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC |
+            CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID |
+            CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
+            CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
+        .features[FEAT_7_0_EBX] =
+            CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_RDSEED |
+            CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_SMEP |
+            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_FSGSBASE,
+        /* missing: CPUID_7_0_ECX_OSPKE */
+        .features[FEAT_7_0_ECX] =
+            CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP,
+        .features[FEAT_7_0_EDX] =
+            CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL,
+        .features[FEAT_8000_0001_EDX] =
+            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
+            CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
+        .features[FEAT_8000_0001_ECX] =
+            CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
+        .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC,
+        /*
+         * TODO: When the Linux kernel introduces other existing definitions
+         * for this leaf, remember to update the definitions here.
+         */
+        .features[FEAT_C000_0001_EDX] =
+            CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM |
+            CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE |
+            CPUID_C000_0001_EDX_ACE2 |
+            CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT |
+            CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE,
+        .features[FEAT_XSAVE] =
+            CPUID_XSAVE_XSAVEOPT,
+        .features[FEAT_ARCH_CAPABILITIES] =
+            MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY |
+            MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO |
+            MSR_ARCH_CAP_SSB_NO,
+        .features[FEAT_VMX_PROCBASED_CTLS] =
+            VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING |
+            VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING |
+            VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING |
+            VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING |
+            VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITING |
+            VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW |
+            VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITING |
+            VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
+            VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAPS |
+            VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
+            VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
+        /*
+         * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING,
+         * VMX_SECONDARY_EXEC_TSC_SCALING
+         */
+        .features[FEAT_VMX_SECONDARY_CTLS] =
+            VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
+            VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
+            VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID |
+            VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
+            VMX_SECONDARY_EXEC_WBINVD_EXITING |
+            VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
+            VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
+            VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
+            VMX_SECONDARY_EXEC_RDRAND_EXITING |
+            VMX_SECONDARY_EXEC_ENABLE_INVPCID |
+            VMX_SECONDARY_EXEC_ENABLE_VMFUNC |
+            VMX_SECONDARY_EXEC_SHADOW_VMCS |
+            VMX_SECONDARY_EXEC_ENABLE_PML,
+        .features[FEAT_VMX_PINBASED_CTLS] =
+            VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
+            VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
+            VMX_PIN_BASED_POSTED_INTR,
+        .features[FEAT_VMX_EXIT_CTLS] =
+            VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE |
+            VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
+            VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
+            VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
+            VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
+        /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */
+        .features[FEAT_VMX_ENTRY_CTLS] =
+            VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
+            VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
+            VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
+        /*
+         * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN,
+         * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI
+         */
+        .features[FEAT_VMX_MISC] =
+            MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
+            MSR_VMX_MISC_VMWRITE_VMEXIT,
+        /* missing: MSR_VMX_EPT_UC */
+        .features[FEAT_VMX_EPT_VPID_CAPS] =
+            MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 |
+            MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
+            MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
+            MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
+            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID |
+            MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
+            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
+        .features[FEAT_VMX_BASIC] =
+            MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
+        .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
+        .xlevel = 0x80000008,
+        .model_id = "Zhaoxin Shijidadao-Client Processor",
+        .cache_info = &shijidadao_cache_info,
+        .versions = (X86CPUVersionDefinition[]) {
+            {
+                .version = 1,
+                .props = (PropValue[]) {
+                    { "x-force-cpuid-0x1f", "on" },
+                    { "smap", "on" },
+                    { /* end of list */ }
+                },
+            },
+            {
+                .version = 2,
+                .note = "with more XSAVE features",
+                .props = (PropValue[]) {
+                    { "xsavec", "on" },
+                    { "xgetbv1", "on" },
+                    { "xsaves", "on"},
+                    { "vmx-xsaves", "on"},
+                    { "smap", "off" },
+                    { /* end of list */ }
+                },
+            },
+            { /* end of list */ }
+        }
+    },
 };
 
 /*
-- 
2.34.1



^ permalink raw reply related	[flat|nested] 8+ messages in thread

* [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server CPU model
  2025-09-23  2:11 [PATCH 0/3] target/i386: Add support for Zhaoxin Shijidadao vCPU models Ewan Hai
  2025-09-23  2:11 ` [PATCH 1/3] target/i386: Add cache model for Zhaoxin Shijidadao vCPUs Ewan Hai
  2025-09-23  2:11 ` [PATCH 2/3] target/i386: Introduce Zhaoxin Shijidadao-Client CPU model Ewan Hai
@ 2025-09-23  2:11 ` Ewan Hai
  2025-10-24  7:15   ` Zhao Liu
  2025-10-24  7:18   ` [PATCH] i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f Zhao Liu
  2 siblings, 2 replies; 8+ messages in thread
From: Ewan Hai @ 2025-09-23  2:11 UTC (permalink / raw)
  To: pbonzini, zhao1.liu; +Cc: qemu-devel

Shijidadao-Server hardware enables IA32_CORE_CAPABILITIES and relies on
the SPLIT_LOCK_DETECT feature. When the kernel has not yet virtualized
this MSR, KVM filters the capability and QEMU emits a warning.

This patch retains the core-capability bit in the CPU model so it will
take effect once KVM support becomes available.

In QEMU, vCPU models default to '.version = 1'. Since there is currently
no '.features[index]' mapping for the "x-force-cpuid-0x1f" property, this
patch adds that property to the v1 version of the model.

Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 target/i386/cpu.c | 139 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 139 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d17284e300..197bdefc2f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6894,6 +6894,145 @@ static const X86CPUDefinition builtin_x86_defs[] = {
             { /* end of list */ }
         }
     },
+    {
+        .name = "Shijidadao-Server",
+        .level = 0x1f,
+        .vendor = CPUID_VENDOR_ZHAOXIN1,
+        .family = 7,
+        .model = 0x7b,
+        .stepping = 0,
+        /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */
+        .features[FEAT_1_EDX] =
+            CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+            CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
+            CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
+            CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
+            CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87,
+        /*
+         * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2,
+         * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX
+         */
+        .features[FEAT_1_ECX] =
+            CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
+            CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER |
+            CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC |
+            CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID |
+            CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
+            CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
+        .features[FEAT_7_0_EBX] =
+            CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_RDSEED |
+            CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_SMEP |
+            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_FSGSBASE,
+        /* missing: CPUID_7_0_ECX_OSPKE */
+        .features[FEAT_7_0_ECX] =
+            CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP,
+        .features[FEAT_7_0_EDX] =
+            CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL |
+            CPUID_7_0_EDX_CORE_CAPABILITY,
+        .features[FEAT_CORE_CAPABILITY] =
+            MSR_CORE_CAP_SPLIT_LOCK_DETECT,
+        .features[FEAT_8000_0001_EDX] =
+            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
+            CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
+        .features[FEAT_8000_0001_ECX] =
+            CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
+        .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC,
+        /*
+         * TODO: When the Linux kernel introduces other existing definitions
+         * for this leaf, remember to update the definitions here.
+         */
+        .features[FEAT_C000_0001_EDX] =
+            CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM |
+            CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE |
+            CPUID_C000_0001_EDX_ACE2 |
+            CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT |
+            CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE,
+        .features[FEAT_XSAVE] =
+            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1 |
+            CPUID_XSAVE_XSAVES,
+        .features[FEAT_ARCH_CAPABILITIES] =
+            MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY |
+            MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO |
+            MSR_ARCH_CAP_SSB_NO,
+        .features[FEAT_VMX_PROCBASED_CTLS] =
+            VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING |
+            VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING |
+            VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING |
+            VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING |
+            VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITING |
+            VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW |
+            VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITING |
+            VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
+            VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAPS |
+            VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
+            VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
+        /*
+         * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING,
+         * VMX_SECONDARY_EXEC_TSC_SCALING
+         */
+        .features[FEAT_VMX_SECONDARY_CTLS] =
+            VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
+            VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
+            VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID |
+            VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
+            VMX_SECONDARY_EXEC_WBINVD_EXITING |
+            VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
+            VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
+            VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
+            VMX_SECONDARY_EXEC_RDRAND_EXITING |
+            VMX_SECONDARY_EXEC_ENABLE_INVPCID |
+            VMX_SECONDARY_EXEC_ENABLE_VMFUNC |
+            VMX_SECONDARY_EXEC_SHADOW_VMCS |
+            VMX_SECONDARY_EXEC_XSAVES      |
+            VMX_SECONDARY_EXEC_ENABLE_PML,
+        .features[FEAT_VMX_PINBASED_CTLS] =
+            VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
+            VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
+            VMX_PIN_BASED_POSTED_INTR,
+        .features[FEAT_VMX_EXIT_CTLS] =
+            VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE |
+            VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
+            VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
+            VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
+            VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
+        /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */
+        .features[FEAT_VMX_ENTRY_CTLS] =
+            VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
+            VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
+            VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
+        /*
+         * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN,
+         * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI
+         */
+        .features[FEAT_VMX_MISC] =
+            MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
+            MSR_VMX_MISC_VMWRITE_VMEXIT,
+        /* missing: MSR_VMX_EPT_UC */
+        .features[FEAT_VMX_EPT_VPID_CAPS] =
+            MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 |
+            MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
+            MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
+            MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
+            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID |
+            MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
+            MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
+        .features[FEAT_VMX_BASIC] =
+            MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
+        .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
+        .xlevel = 0x80000008,
+        .model_id = "Zhaoxin Shijidadao Processor",
+        .cache_info = &shijidadao_cache_info,
+        .versions = (X86CPUVersionDefinition[]) {
+            {
+                .version = 1,
+                .props = (PropValue[]) {
+                    { "x-force-cpuid-0x1f", "on" },
+                    { /* end of list */ }
+                },
+            },
+            { /* end of list */ }
+        }
+    },
 };
 
 /*
-- 
2.34.1



^ permalink raw reply related	[flat|nested] 8+ messages in thread

* Re: [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server CPU model
  2025-09-23  2:11 ` [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server " Ewan Hai
@ 2025-10-24  7:15   ` Zhao Liu
  2025-10-27  3:42     ` Ewan Hai
  2025-10-24  7:18   ` [PATCH] i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f Zhao Liu
  1 sibling, 1 reply; 8+ messages in thread
From: Zhao Liu @ 2025-10-24  7:15 UTC (permalink / raw)
  To: Ewan Hai; +Cc: pbonzini, qemu-devel

On Mon, Sep 22, 2025 at 10:11:33PM -0400, Ewan Hai wrote:
> Date: Mon, 22 Sep 2025 22:11:33 -0400
> From: Ewan Hai <ewanhai-oc@zhaoxin.com>
> Subject: [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server CPU
>  model
> X-Mailer: git-send-email 2.34.1
> 
> Shijidadao-Server hardware enables IA32_CORE_CAPABILITIES and relies on
> the SPLIT_LOCK_DETECT feature. When the kernel has not yet virtualized
> this MSR, KVM filters the capability and QEMU emits a warning.
> 
> This patch retains the core-capability bit in the CPU model so it will
> take effect once KVM support becomes available.
> 
> In QEMU, vCPU models default to '.version = 1'. Since there is currently
> no '.features[index]' mapping for the "x-force-cpuid-0x1f" property, this
> patch adds that property to the v1 version of the model.

I'm preparing the CPU model for Diamond Rapids, and also meet this
issue.

Well, I happen to have a patch for this and I think you could give it
a try. :)

Thanks,
Zhao



^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server CPU model
  2025-10-24  7:15   ` Zhao Liu
@ 2025-10-27  3:42     ` Ewan Hai
  2025-10-27  6:14       ` Zhao Liu
  0 siblings, 1 reply; 8+ messages in thread
From: Ewan Hai @ 2025-10-27  3:42 UTC (permalink / raw)
  To: Zhao Liu; +Cc: pbonzini, qemu-devel, ewanhai, cobechen

On 10/24/25 3:15 PM, Zhao Liu wrote:
> 
> 
> On Mon, Sep 22, 2025 at 10:11:33PM -0400, Ewan Hai wrote:
>> Date: Mon, 22 Sep 2025 22:11:33 -0400
>> From: Ewan Hai <ewanhai-oc@zhaoxin.com>
>> Subject: [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server CPU
>>  model
>> X-Mailer: git-send-email 2.34.1
>>
>> Shijidadao-Server hardware enables IA32_CORE_CAPABILITIES and relies on
>> the SPLIT_LOCK_DETECT feature. When the kernel has not yet virtualized
>> this MSR, KVM filters the capability and QEMU emits a warning.
>>
>> This patch retains the core-capability bit in the CPU model so it will
>> take effect once KVM support becomes available.
>>
>> In QEMU, vCPU models default to '.version = 1'. Since there is currently
>> no '.features[index]' mapping for the "x-force-cpuid-0x1f" property, this
>> patch adds that property to the v1 version of the model.
> 
> I'm preparing the CPU model for Diamond Rapids, and also meet this
> issue.
> 
> Well, I happen to have a patch for this and I think you could give it
> a try. :)

That's good news. I'll test your patch and update mine accordingly.
When I send out v2, should I note in the cover letter that my patches are based
on your "0x1f option" patch?



^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server CPU model
  2025-10-27  3:42     ` Ewan Hai
@ 2025-10-27  6:14       ` Zhao Liu
  0 siblings, 0 replies; 8+ messages in thread
From: Zhao Liu @ 2025-10-27  6:14 UTC (permalink / raw)
  To: Ewan Hai; +Cc: pbonzini, qemu-devel, ewanhai, cobechen

> >> In QEMU, vCPU models default to '.version = 1'. Since there is currently
> >> no '.features[index]' mapping for the "x-force-cpuid-0x1f" property, this
> >> patch adds that property to the v1 version of the model.
> > 
> > I'm preparing the CPU model for Diamond Rapids, and also meet this
> > issue.
> > 
> > Well, I happen to have a patch for this and I think you could give it
> > a try. :)
> 
> That's good news. I'll test your patch and update mine accordingly.
> When I send out v2, should I note in the cover letter that my patches are based
> on your "0x1f option" patch?

Please feel free to pick that patch into your series.

Regards,
Zhao




^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH] i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f
  2025-09-23  2:11 ` [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server " Ewan Hai
  2025-10-24  7:15   ` Zhao Liu
@ 2025-10-24  7:18   ` Zhao Liu
  1 sibling, 0 replies; 8+ messages in thread
From: Zhao Liu @ 2025-10-24  7:18 UTC (permalink / raw)
  To: Ewan Hai; +Cc: pbonzini, qemu-devel

Many Intel and Zhaoxin CPUs enable CPUID 0x1f by default to encode CPU
topology information.

Add the "cpuid_0x1f" option to X86CPUDefinition to allow named CPU
models to configure CPUID 0x1f from the start, thereby forcing 0x1f
to be present for guest.

With this option, there's no need to explicitly add v1 model to an
unversioned CPU model for explicitly enabling the x-force-cpuid-0x1f
property.

Tested-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
 target/i386/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 175054fdb322..56c1030a8627 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2307,6 +2307,12 @@ typedef struct X86CPUDefinition {
     int model;
     int stepping;
     uint8_t avx10_version;
+    /*
+     * Whether to present CPUID 0x1f by default.
+     * If true, encode CPU topology in 0x1f leaf even if there's no
+     * extended topology levels.
+     */
+    bool cpuid_0x1f;
     FeatureWordArray features;
     const char *model_id;
     const CPUCaches *const cache_info;
@@ -8092,6 +8098,10 @@ static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model)
                                  &error_abort);
     }

+    if (def->cpuid_0x1f) {
+        object_property_set_bool(OBJECT(cpu), "x-force-cpuid-0x1f", def->cpuid_0x1f,
+                                 &error_abort);
+    }
     x86_cpu_apply_version_props(cpu, model);

     /*
--
2.34.1




^ permalink raw reply related	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2025-10-27  5:52 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-09-23  2:11 [PATCH 0/3] target/i386: Add support for Zhaoxin Shijidadao vCPU models Ewan Hai
2025-09-23  2:11 ` [PATCH 1/3] target/i386: Add cache model for Zhaoxin Shijidadao vCPUs Ewan Hai
2025-09-23  2:11 ` [PATCH 2/3] target/i386: Introduce Zhaoxin Shijidadao-Client CPU model Ewan Hai
2025-09-23  2:11 ` [PATCH 3/3] target/i386: Introduce Zhaoxin Shijidadao-Server " Ewan Hai
2025-10-24  7:15   ` Zhao Liu
2025-10-27  3:42     ` Ewan Hai
2025-10-27  6:14       ` Zhao Liu
2025-10-24  7:18   ` [PATCH] i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f Zhao Liu

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