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d="scan'208";a="185678709" Received: from liuzhao-optiplex-7080.sh.intel.com (HELO localhost) ([10.239.160.39]) by fmviesa007.fm.intel.com with ESMTP; 30 Oct 2025 08:42:18 -0700 Date: Fri, 31 Oct 2025 00:04:30 +0800 From: Zhao Liu To: Xiaoyao Li Cc: Paolo Bonzini , Marcelo Tosatti , qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Farrah Chen , Yang Weijiang Subject: Re: [PATCH v3 15/20] i386/machine: Add vmstate for cet-ss and cet-ibt Message-ID: References: <20251024065632.1448606-1-zhao1.liu@intel.com> <20251024065632.1448606-16-zhao1.liu@intel.com> <445462e9-22e5-4e8b-999e-7be468731752@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <445462e9-22e5-4e8b-999e-7be468731752@intel.com> Received-SPF: pass client-ip=198.175.65.12; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Oct 28, 2025 at 04:29:58PM +0800, Xiaoyao Li wrote: > Date: Tue, 28 Oct 2025 16:29:58 +0800 > From: Xiaoyao Li > Subject: Re: [PATCH v3 15/20] i386/machine: Add vmstate for cet-ss and > cet-ibt > > On 10/24/2025 2:56 PM, Zhao Liu wrote: > > From: Yang Weijiang > > > > Add vmstates for cet-ss and cet-ibt > > > > Tested-by: Farrah Chen > > Signed-off-by: Yang Weijiang > > Co-developed-by: Chao Gao > > Signed-off-by: Chao Gao > > Co-developed-by: Zhao Liu > > Signed-off-by: Zhao Liu > > --- > > Changes Since v2: > > - Split a subsection "vmstate_ss" since shstk is user-configurable. > > --- > > target/i386/machine.c | 53 +++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 53 insertions(+) > > > > diff --git a/target/i386/machine.c b/target/i386/machine.c > > index 45b7cea80aa7..3ad07ec82428 100644 > > --- a/target/i386/machine.c > > +++ b/target/i386/machine.c > > @@ -1668,6 +1668,58 @@ static const VMStateDescription vmstate_triple_fault = { > > } > > }; > > +static bool shstk_needed(void *opaque) > > +{ > > + X86CPU *cpu = opaque; > > + CPUX86State *env = &cpu->env; > > + > > + return !!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK); > > +} > > + > > +static const VMStateDescription vmstate_ss = { > > + .name = "cpu/cet_ss", > > + .version_id = 1, > > + .minimum_version_id = 1, > > + .needed = shstk_needed, > > + .fields = (VMStateField[]) { > > + VMSTATE_UINT64(env.pl0_ssp, X86CPU), > > + VMSTATE_UINT64(env.pl1_ssp, X86CPU), > > + VMSTATE_UINT64(env.pl2_ssp, X86CPU), > > + VMSTATE_UINT64(env.pl3_ssp, X86CPU), > > +#ifdef TARGET_X86_64 > > + /* This MSR is only present on Intel 64 architecture. */ > > + VMSTATE_UINT64(env.int_ssp_table, X86CPU), > > +#endif > > It seems we need to split int_ssp_table into a separate vmstate_* > > Its .needed function needs to check both CPUID_7_0_ECX_CET_SHSTK && > CPUID_EXT2_LM. Ok, will split this entry into a subsection. Thanks. > > + VMSTATE_UINT64(env.guest_ssp, X86CPU), > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > +static bool cet_needed(void *opaque) > > +{ > > + X86CPU *cpu = opaque; > > + CPUX86State *env = &cpu->env; > > + > > + return !!((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) || > > + (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT)); > > +} > > + > > +static const VMStateDescription vmstate_cet = { > > + .name = "cpu/cet", > > + .version_id = 1, > > + .minimum_version_id = 1, > > + .needed = cet_needed, > > + .fields = (VMStateField[]) { > > + VMSTATE_UINT64(env.u_cet, X86CPU), > > + VMSTATE_UINT64(env.s_cet, X86CPU), > > + VMSTATE_END_OF_LIST() > > + }, > > + .subsections = (const VMStateDescription * const []) { > > + &vmstate_ss, here: ^^^^^^^^^^^^^ > > + NULL, > > + }, > > +}; > > + > > const VMStateDescription vmstate_x86_cpu = { > > .name = "cpu", > > .version_id = 12, > > @@ -1817,6 +1869,7 @@ const VMStateDescription vmstate_x86_cpu = { > > #endif > > &vmstate_arch_lbr, > > &vmstate_triple_fault, > > + &vmstate_cet, > > missing &vmstate_ss I made vmstate_ss as a subsection in vmstate_cet Regards, Zhao