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[94.175.9.129]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42fa8b85f81sm4448039f8f.21.2025.12.11.00.08.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Dec 2025 00:08:15 -0800 (PST) Date: Thu, 11 Dec 2025 08:08:14 +0000 From: Stafford Horne To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: Arnd Bergmann , Peter Maydell , Geert Uytterhoeven , Joel Stanley , "Jason A. Donenfeld" , Openrisc , QEMU Development , qemu-riscv Subject: Re: [RFC PATCH 3/3] hw/openrisc: Add the OpenRISC virtual machine Message-ID: References: <59727ca7-9f17-4688-8212-9c37271af41b@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <59727ca7-9f17-4688-8212-9c37271af41b@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=shorne@gmail.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Dec 10, 2025 at 06:22:11AM +0100, Philippe Mathieu-Daudé wrote: > On 7/6/22 16:08, Arnd Bergmann wrote: > > On Tue, Jun 7, 2022 at 2:12 PM Stafford Horne wrote: > > > On Tue, Jun 07, 2022 at 11:43:08AM +0100, Peter Maydell wrote: > > > > > > However, in a followup mail from Laurent we see: > > > > > > https://lore.kernel.org/lkml/cb884368-0226-e913-80d2-62d2b7b2e761@vivier.eu/ > > > > > > The reference document[1] doesn't define the endianness of goldfish. > > > > > > [1] https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT > > > > > > > > > The documentation does not clearly specify it. So maybe maybe or1k should just > > > be updated on the linux side and add gf_ioread32/gf_iowrite32 big-endian > > > accessors. > > > > I don't think it makes any sense to use big-endian for a new > > architecture, just use > > the default little-endian implementation on the linux side, and change > > the qemu code > > to have the backward-compatibility hack for m68k while using big-endian for > > the rest. > > Hitting this thread 3 years latter, suffering with endiannes. Sigh. What is the issue this is causing? > Back to OpenRISC virt machine, it is unfortunate it picked the > TYPE_SIFIVE_TEST virtual device (expected to be little-endian) > instead of the TYPE_VIRT_CTRL one (expected to be big-endian, > like OpenRISC). > > Fortunately (to me) OpenRISC virt machine exposes the TYPE_SIFIVE_TEST > virtual device via device tree, and make its endianness explicitly to > little order. > > Stafford, is it too late to use the TYPE_VIRT_CTRL? We could map it > as a secondary reset device at another address, deprecate the use of > the mapped SIFIVE_TEST then remove it. I think its ok to add a second device if that will help you. But, it will take time to deco the old device as people may be running old kernels, with old device trees that expect the SIFIVE device for some time. -Stafford