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From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Bernhard Beschow <shentey@gmail.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Eduardo Habkost <eduardo@habkost.net>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Subject: [PULL v3 50/62] hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine
Date: Sun, 22 Oct 2023 05:25:27 -0400	[thread overview]
Message-ID: <aa0c9aec575f6dba4e6548ad9e5de1b1899d843e.1697966402.git.mst@redhat.com> (raw)
In-Reply-To: <cover.1697966402.git.mst@redhat.com>

From: Bernhard Beschow <shentey@gmail.com>

QEMU's PIIX3 implementation actually models the real PIIX4, but with different
PCI IDs. Usually, guests deal just fine with it. Still, in order to provide a
more consistent illusion to guests, allow QEMU's PIIX4 implementation to be used
in the PC machine.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-30-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/i386/pc.h                 |  2 +
 hw/i386/pc.c                         |  1 +
 hw/i386/pc_piix.c                    | 61 +++++++++++++++++++++++++++-
 docs/system/target-i386-desc.rst.inc |  8 ++++
 4 files changed, 71 insertions(+), 1 deletion(-)

diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index bec38cb92c..29a9724524 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -42,6 +42,7 @@ typedef struct PCMachineState {
     uint64_t max_ram_below_4g;
     OnOffAuto vmport;
     SmbiosEntryPointType smbios_entry_point_type;
+    const char *south_bridge;
 
     bool acpi_build_enabled;
     bool smbus_enabled;
@@ -92,6 +93,7 @@ struct PCMachineClass {
     /* Device configuration: */
     bool pci_enabled;
     bool kvmclock_enabled;
+    const char *default_south_bridge;
 
     /* Compat options: */
 
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 355e1b7cf6..6293f57a0c 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1706,6 +1706,7 @@ static void pc_machine_initfn(Object *obj)
 #endif /* CONFIG_VMPORT */
     pcms->max_ram_below_4g = 0; /* use default */
     pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
+    pcms->south_bridge = pcmc->default_south_bridge;
 
     /* acpi build is enabled by default if machine supports it */
     pcms->acpi_build_enabled = pcmc->has_acpi_build;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index e38942a3c3..334d9a0299 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -262,7 +262,7 @@ static void pc_init1(MachineState *machine,
         DeviceState *dev;
         size_t i;
 
-        pci_dev = pci_new_multifunction(-1, TYPE_PIIX3_DEVICE);
+        pci_dev = pci_new_multifunction(-1, pcms->south_bridge);
         object_property_set_bool(OBJECT(pci_dev), "has-usb",
                                  machine_usb(machine), &error_abort);
         object_property_set_bool(OBJECT(pci_dev), "has-acpi",
@@ -394,6 +394,56 @@ static void pc_init1(MachineState *machine,
     }
 }
 
+typedef enum PCSouthBridgeOption {
+    PC_SOUTH_BRIDGE_OPTION_PIIX3,
+    PC_SOUTH_BRIDGE_OPTION_PIIX4,
+    PC_SOUTH_BRIDGE_OPTION_MAX,
+} PCSouthBridgeOption;
+
+static const QEnumLookup PCSouthBridgeOption_lookup = {
+    .array = (const char *const[]) {
+        [PC_SOUTH_BRIDGE_OPTION_PIIX3] = TYPE_PIIX3_DEVICE,
+        [PC_SOUTH_BRIDGE_OPTION_PIIX4] = TYPE_PIIX4_PCI_DEVICE,
+    },
+    .size = PC_SOUTH_BRIDGE_OPTION_MAX
+};
+
+#define NotifyVmexitOption_str(val) \
+    qapi_enum_lookup(&NotifyVmexitOption_lookup, (val))
+
+static int pc_get_south_bridge(Object *obj, Error **errp)
+{
+    PCMachineState *pcms = PC_MACHINE(obj);
+    int i;
+
+    for (i = 0; i < PCSouthBridgeOption_lookup.size; i++) {
+        if (g_strcmp0(PCSouthBridgeOption_lookup.array[i],
+                      pcms->south_bridge) == 0) {
+            return i;
+        }
+    }
+
+    error_setg(errp, "Invalid south bridge value set");
+    return 0;
+}
+
+static void pc_set_south_bridge(Object *obj, int value, Error **errp)
+{
+    PCMachineState *pcms = PC_MACHINE(obj);
+
+    if (value < 0) {
+        error_setg(errp, "Value can't be negative");
+        return;
+    }
+
+    if (value >= PCSouthBridgeOption_lookup.size) {
+        error_setg(errp, "Value too big");
+        return;
+    }
+
+    pcms->south_bridge = PCSouthBridgeOption_lookup.array[value];
+}
+
 /* Looking for a pc_compat_2_4() function? It doesn't exist.
  * pc_compat_*() functions that run on machine-init time and
  * change global QEMU state are deprecated. Please don't create
@@ -473,6 +523,8 @@ static void pc_xen_hvm_init(MachineState *machine)
 static void pc_i440fx_machine_options(MachineClass *m)
 {
     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
+    ObjectClass *oc = OBJECT_CLASS(m);
+    pcmc->default_south_bridge = TYPE_PIIX3_DEVICE;
     pcmc->pci_root_uid = 0;
     pcmc->default_cpu_version = 1;
 
@@ -484,6 +536,13 @@ static void pc_i440fx_machine_options(MachineClass *m)
     m->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL);
     machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
     machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE);
+
+    object_class_property_add_enum(oc, "x-south-bridge", "PCSouthBridgeOption",
+                                   &PCSouthBridgeOption_lookup,
+                                   pc_get_south_bridge,
+                                   pc_set_south_bridge);
+    object_class_property_set_description(oc, "x-south-bridge",
+                                     "Use a different south bridge than PIIX3");
 }
 
 static void pc_i440fx_8_2_machine_options(MachineClass *m)
diff --git a/docs/system/target-i386-desc.rst.inc b/docs/system/target-i386-desc.rst.inc
index 7d1fffacbe..5ebbcda9db 100644
--- a/docs/system/target-i386-desc.rst.inc
+++ b/docs/system/target-i386-desc.rst.inc
@@ -71,3 +71,11 @@ machine property, i.e.
    |qemu_system_x86| some.img \
    -audiodev <backend>,id=<name> \
    -machine pcspk-audiodev=<name>
+
+Machine-specific options
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+It supports the following machine-specific options:
+
+- ``x-south-bridge=PIIX3|piix4-isa`` (Experimental option to select a particular
+  south bridge. Default: ``PIIX3``)
-- 
MST



  parent reply	other threads:[~2023-10-22  9:27 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-22  9:21 [PULL v3 00/62] virtio,pc,pci: features, cleanups Michael S. Tsirkin
2023-10-22  9:21 ` [PULL v3 01/62] vdpa: Use iovec for vhost_vdpa_net_cvq_add() Michael S. Tsirkin
2023-10-22  9:22 ` [PULL v3 02/62] vdpa: Avoid using vhost_vdpa_net_load_*() outside vhost_vdpa_net_load() Michael S. Tsirkin
2023-10-22  9:22 ` [PULL v3 03/62] vdpa: Check device ack in vhost_vdpa_net_load_rx_mode() Michael S. Tsirkin
2023-10-22  9:22 ` [PULL v3 04/62] vdpa: Move vhost_svq_poll() to the caller of vhost_vdpa_net_cvq_add() Michael S. Tsirkin
2023-10-22  9:22 ` [PULL v3 05/62] vdpa: Introduce cursors to vhost_vdpa_net_loadx() Michael S. Tsirkin
2023-10-22  9:22 ` [PULL v3 06/62] vhost: Expose vhost_svq_available_slots() Michael S. Tsirkin
2023-10-22  9:22 ` [PULL v3 07/62] vdpa: Send cvq state load commands in parallel Michael S. Tsirkin
2023-10-22  9:22 ` [PULL v3 08/62] vhost-user: strip superfluous whitespace Michael S. Tsirkin
2023-10-22  9:22 ` [PULL v3 09/62] vhost-user: tighten "reply_supported" scope in "set_vring_addr" Michael S. Tsirkin
2023-10-22  9:22 ` [PULL v3 10/62] vhost-user: factor out "vhost_user_write_sync" Michael S. Tsirkin
2023-10-22  9:22 ` [PULL v3 11/62] vhost-user: flatten "enforce_reply" into "vhost_user_write_sync" Michael S. Tsirkin
2023-10-22  9:22 ` [PULL v3 12/62] vhost-user: hoist "write_sync", "get_features", "get_u64" Michael S. Tsirkin
2023-10-22  9:22 ` [PULL v3 13/62] vhost-user: allow "vhost_set_vring" to wait for a reply Michael S. Tsirkin
2023-10-22  9:22 ` [PULL v3 14/62] vhost-user: call VHOST_USER_SET_VRING_ENABLE synchronously Michael S. Tsirkin
2023-10-22  9:22 ` [PULL v3 15/62] memory: initialize 'fv' in MemoryRegionCache to make Coverity happy Michael S. Tsirkin
2023-10-22  9:22 ` [PULL v3 16/62] vhost-user: do not send RESET_OWNER on device reset Michael S. Tsirkin
2023-10-22  9:23 ` [PULL v3 17/62] vhost-backend: remove vhost_kernel_reset_device() Michael S. Tsirkin
2023-10-22  9:23 ` [PULL v3 18/62] virtio: call ->vhost_reset_device() during reset Michael S. Tsirkin
2023-10-22  9:23 ` [PULL v3 19/62] hw/i386/acpi-build: Remove build-time assertion on PIIX/ICH9 reset registers being identical Michael S. Tsirkin
2023-10-22  9:23 ` [PULL v3 20/62] timer/i8254: Fix one shot PIT mode Michael S. Tsirkin
2023-10-22  9:23 ` [PULL v3 21/62] hw/display: fix memleak from virtio_add_resource Michael S. Tsirkin
2023-10-24  6:19   ` Michael Tokarev
2023-10-22  9:23 ` [PULL v3 22/62] hw/i386/pc: Merge two if statements into one Michael S. Tsirkin
2023-10-22  9:23 ` [PULL v3 23/62] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge Michael S. Tsirkin
2023-10-22  9:23 ` [PULL v3 24/62] hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize() Michael S. Tsirkin
2023-10-22  9:23 ` [PULL v3 25/62] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS Michael S. Tsirkin
2023-10-22  9:23 ` [PULL v3 26/62] hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property Michael S. Tsirkin
2023-10-22  9:23 ` [PULL v3 27/62] hw/i386/pc_piix: Remove redundant "piix3" variable Michael S. Tsirkin
2023-10-22  9:23 ` [PULL v3 28/62] hw/isa/piix3: Rename "pic" attribute to "isa_irqs_in" Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 29/62] hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize() Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 30/62] hw/isa/piix3: Wire PIC IRQs to ISA bus in host device Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 31/62] hw/i386/pc: Wire RTC ISA IRQs in south bridges Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 32/62] hw/isa/piix3: Create IDE controller in host device Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 33/62] hw/isa/piix3: Create USB " Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 34/62] hw/isa/piix3: Create power management " Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 35/62] hw/isa/piix3: Drop the "3" from PIIX base class name Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 36/62] hw/isa/piix4: Remove unused inbound ISA interrupt lines Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 37/62] hw/isa/piix4: Rename "isa" attribute to "isa_irqs_in" Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 38/62] hw/isa/piix4: Rename reset control operations to match PIIX3 Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 39/62] hw/isa/piix4: Reuse struct PIIXState from PIIX3 Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 40/62] hw/isa/piix3: Merge hw/isa/piix4.c Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 41/62] hw/isa/piix: Allow for optional PIC creation in PIIX3 Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 42/62] hw/isa/piix: Allow for optional PIT " Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 43/62] hw/isa/piix: Harmonize names of reset control memory regions Michael S. Tsirkin
2023-10-22  9:24 ` [PULL v3 44/62] hw/isa/piix: Share PIIX3's base class with PIIX4 Michael S. Tsirkin
2023-10-22  9:25 ` [PULL v3 45/62] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 Michael S. Tsirkin
2023-10-22  9:25 ` [PULL v3 46/62] hw/isa/piix: Rename functions to be shared for PCI interrupt triggering Michael S. Tsirkin
2023-10-22  9:25 ` [PULL v3 47/62] hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4 Michael S. Tsirkin
2023-10-22  9:25 ` [PULL v3 48/62] hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring Michael S. Tsirkin
2023-10-22  9:25 ` [PULL v3 49/62] hw/isa/piix: Implement multi-process QEMU support also for PIIX4 Michael S. Tsirkin
2023-10-22  9:25 ` Michael S. Tsirkin [this message]
2023-10-22  9:25 ` [PULL v3 51/62] vhost-user-common: send get_inflight_fd once Michael S. Tsirkin
2023-10-22  9:25 ` [PULL v3 52/62] vhost: move and rename the conn retry times Michael S. Tsirkin
2023-10-22  9:25 ` [PULL v3 53/62] vhost-user-scsi: support reconnect to backend Michael S. Tsirkin
2023-10-22  9:25 ` [PULL v3 54/62] vhost-user-scsi: start vhost when guest kicks Michael S. Tsirkin
2023-10-22  9:26 ` [PULL v3 55/62] vhost-user: fix lost reconnect Michael S. Tsirkin
2023-10-22  9:26 ` [PULL v3 56/62] hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range Michael S. Tsirkin
2023-10-22  9:26 ` [PULL v3 57/62] tests/acpi: Allow update of DSDT.cxl Michael S. Tsirkin
2023-10-22  9:26 ` [PULL v3 58/62] hw/cxl: Add QTG _DSM support for ACPI0017 device Michael S. Tsirkin
2023-10-22  9:26 ` [PULL v3 59/62] tests/acpi: Update DSDT.cxl with QTG DSM Michael S. Tsirkin
2023-10-22  9:26 ` [PULL v3 60/62] vhost-user: Fix protocol feature bit conflict Michael S. Tsirkin
2023-10-22  9:26 ` [PULL v3 61/62] MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section Michael S. Tsirkin
2023-10-22  9:26 ` [PULL v3 62/62] intel-iommu: Report interrupt remapping faults, fix return value Michael S. Tsirkin
2023-10-24  1:15 ` [PULL v3 00/62] virtio,pc,pci: features, cleanups Stefan Hajnoczi

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